| Message ID | 1617990965-35337-3-git-send-email-radhey.shyam.pandey@xilinx.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | Xilinx DMA enhancements and optimization | expand |
On Fri, 09 Apr 2021 23:26:00 +0530, Radhey Shyam Pandey wrote: > Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt > timeout value and causes the DMA engine to generate an interrupt after the > delay time period has expired. Timer begins counting at the end of a packet > and resets with receipt of a new packet or a timeout event occurs. > > This property is useful when AXI DMA is connected to the streaming IP i.e > axiethernet where inter packet latency is critical while still taking the > benefit of interrupt coalescing. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > Changes for v2: > - New patch. Introduce xlnx,irq-delay property for low latency usecases > --- > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index f5f23a4a4467..96009ced7b29 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -50,7 +50,9 @@ Optional properties for AXI DMA and MCDMA: is missing or invalid then the default value 23 is used. This is the maximum value that is supported by all IP versions. - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. - +- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from + 0-255. Setting this value to zero disables the delay timer interrupt. + 1 timeout interval = 125 * clock period of SG clock. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values:
Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt timeout value and causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs. This property is useful when AXI DMA is connected to the streaming IP i.e axiethernet where inter packet latency is critical while still taking the benefit of interrupt coalescing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> --- Changes for v2: - New patch. Introduce xlnx,irq-delay property for low latency usecases --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)