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Thu, 14 Apr 2022 05:24:33 -0700 Envelope-to: git@xilinx.com, krzk+dt@kernel.org, robh+dt@kernel.org, vkoul@kernel.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.6] (port=53815 helo=xhdvnc106.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1neyWX-0003df-4J; Thu, 14 Apr 2022 05:24:33 -0700 Received: by xhdvnc106.xilinx.com (Postfix, from userid 13245) id 5C97661054; Thu, 14 Apr 2022 17:54:32 +0530 (IST) From: Radhey Shyam Pandey To: , , CC: , , , , , Subject: [PATCH] dt-bindings: dmaengine: xilinx_dma: Add MCMDA channel ID index description Date: Thu, 14 Apr 2022 17:54:21 +0530 Message-ID: <1649939061-6675-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e7647f3a-f5d8-4ced-465c-08da1e11bc46 X-MS-TrafficTypeDiagnostic: CY4PR02MB2263:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 12:24:34.7564 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7647f3a-f5d8-4ced-465c-08da1e11bc46 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0003.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2263 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org MCDMA IP provides up to 16 multiple channels of data movement each on MM2S and S2MM paths. Inline with implementation, in the binding add description for the channel ID start index and mention that it's fixed irrespective of the MCDMA IP configuration(number of read/write channels). Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 325aca52cd43..d1700a5c36bf 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -110,7 +110,11 @@ axi_vdma_0: axivdma@40030000 { Required properties: - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx - channel. + channel. For MCMDA, MM2S channel(write/tx) ID start from + '0' and is in [0-15] range. S2MM channel(read/rx) ID start + from '16' and is in [16-31] range. These channels ID are + fixed irrespective of IP configuration. + - dma-names: a list of DMA channel names, one per "dmas" entry Example: