From patchwork Tue Oct 4 21:43:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 12998722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 430C6C4332F for ; Tue, 4 Oct 2022 21:46:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbiJDVqU (ORCPT ); Tue, 4 Oct 2022 17:46:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232113AbiJDVpr (ORCPT ); Tue, 4 Oct 2022 17:45:47 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2069.outbound.protection.outlook.com [40.107.92.69]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5516BB93; Tue, 4 Oct 2022 14:44:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D+RSS8O+QUiiWlh+stl28rzozpaaykXMsf0ilf/IqmPh8bb9uZN1X7iuKIE5u5XLoK972R6YCdjvAz5kxjEJEA8pvjkehB4/S1wBm8DnfYsNeTOCGw0tXLIgfFSCCXeBY/kHs88wAmiATIifAACK3rW8/VeAm2Lafj2SzxWANaeE32WtnQWp9JSWuqLvqzO1hzGkBs/8KC5SrdBt+QVlIWV2BZnPKlpviajDvucCyuCE2i6p2rlo7TUwerLy40ePOTgIAuUYD+PvzDbaXzmtVA4hqk61cCkML6UrXpxZqX+KIHiWqqQq2DGZfIMzjFnhJ4Mvh/YkzHvVDfbgpbm58A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1/oD35ZtG6ljH3gj2DhHB8dkW90LUj/fUM1nPxvpfYM=; b=mnsk2Vpv7MbC1LgEGYSVuw5kVeK+oKDYhX4JYbBvLxJL5HCIXNRZ1YQ1LcUE8Zn1PEKyjmx6xLisHuSBq9aGsWKfgo0N4R0wiO67SuaUN3eEhG+WhltxiPXQI+hm0hsQZ0Ya8Lx8GooalmaFu2dm+FbngbJrjz3h9XlVubDbkbe99j6Hjk8onyfXPKJKQCVSrcui9N4jbk2FrKM9/Mb9fQ0f79AvJT9ofg7sais1AO39R9gDsfonARifaxeviTrBJ/WVhozgnE+kxU/2NnkNvlWw9eAU/0WkRexUYfWxpV32tkUlay5I7srW6xIQC+8Q77K57RKpkMXuJ6XygcpdsQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1/oD35ZtG6ljH3gj2DhHB8dkW90LUj/fUM1nPxvpfYM=; b=ZmK3Wc/DXXvaQNJkM16mq89I8ra1MzbVMIIWS5q8R/TEPniik6iLyCF2lqp4HtZFEmjGRZxf6Yhp7wTvZ0P1O09q/T7RxFVc3OK1hnhzejY0oNI6d/xxX1AY7s1Pxvg0zuiJ4LYmIAYFd/H1Kf8yxwccUciFUMmM66J5JHpujz8= Received: from BN9P221CA0008.NAMP221.PROD.OUTLOOK.COM (2603:10b6:408:10a::30) by SA1PR12MB6821.namprd12.prod.outlook.com (2603:10b6:806:25c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.17; Tue, 4 Oct 2022 21:44:07 +0000 Received: from BN8NAM11FT116.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10a:cafe::5e) by BN9P221CA0008.outlook.office365.com (2603:10b6:408:10a::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.30 via Frontend Transport; Tue, 4 Oct 2022 21:44:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT116.mail.protection.outlook.com (10.13.176.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Tue, 4 Oct 2022 21:44:07 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 4 Oct 2022 16:44:04 -0500 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 4 Oct 2022 16:44:03 -0500 From: Lizhi Hou To: , , , CC: Lizhi Hou , , , , , Subject: [PATCH V6 XDMA 2/2] dmaengine: xilinx: xdma: Add user logic interrupt support Date: Tue, 4 Oct 2022 14:43:59 -0700 Message-ID: <1664919839-27149-3-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1664919839-27149-1-git-send-email-lizhi.hou@amd.com> References: <1664919839-27149-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT116:EE_|SA1PR12MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: 631136c1-02e3-46eb-d52f-08daa6519078 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xzFcVamIyg0J2Ue9hjDFVMOUQ1o8aYsPMPbm2gVI3STqzyo2ABhss1ZDpILv+R48ovS+iYXG2rWOhYwuA5AEf1Tu9Bd4xVv/osUWl6MdiI6L9OILg+bULl1Tycx2WZyzFLCfzXFgxiqENf31cn3bLoCX8CSFZRw6IXZvLCURQIJzQU56N2tac0TEBiDITyd9cyA8idSVXKDZt6r07b+4AEwLSwEHG0nrPM6mZY9xw1/dN0x3BZ7OTpvXK/Uezj9LotdviErtKiq9iCWaSEzZIM7n8n+x9EPHIWXwJcbmeig1tmEBJIIcoUiNBGAz1+p4yQ7XZ3fdkzT05AHTQ3k6wxBT9OoomJn4E3x7ap1/rXx6cdtzlFXrtcYfXiA+BAdjqLQbo6G1GldLwQvtXQqHhx2pIvrzf8dSJ+gAuO4dpQ9JAzH1Uh55eaNJo1w0s2DUqXP16Wqyp7dEaMnntVnBUKw0b79VAIl7L2d/1m8/LOEX32wIKci8pyEK9I8AwYltP22AnXoUc0+UZqqanIqLM/kkNwQQxbo8LxZ+dXrybmi/QG3n8fAVFSJa40ISGySA5ZjV/lNvL7KvvGOelWoKg033TrtwrvrXV+ftOgFvOcoHSelSvAs6QLXgY4kf/60SdY6778U+WHyPQQY7+lH5lURBzYZER5/mpkiqnCCVaTF1I+abNi96IsCfqzcD8ohAckKvQ9In0R7yN19bdN1GaMZCaxVffV+3RRQQvX7YY2BkNhXHbd6vLvEFkYk+R5nmnhmImb6OYqDFky0HZfN79xoIDAeSnz716a1UKIdZTqaj+4BQIQkyZ938ylduPnCS X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(82310400005)(356005)(110136005)(81166007)(82740400003)(478600001)(316002)(54906003)(44832011)(47076005)(70586007)(86362001)(70206006)(40460700003)(426003)(6666004)(8676002)(4326008)(36756003)(83380400001)(40480700001)(41300700001)(36860700001)(8936002)(336012)(2906002)(26005)(5660300002)(186003)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 21:44:07.2121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 631136c1-02e3-46eb-d52f-08daa6519078 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The Xilinx DMA/Bridge Subsystem for PCIe (XDMA) provides up to 16 user interrupt wires to user logic that generate interrupts to the host. This patch adds APIs to enable/disable user logic interrupt for a given interrupt wire index. Signed-off-by: Lizhi Hou Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Brian Xu --- MAINTAINERS | 1 + drivers/dma/xilinx/xdma.c | 87 ++++++++++++++++++++++++++++++++++++ include/linux/dma/amd_xdma.h | 16 +++++++ 3 files changed, 104 insertions(+) create mode 100644 include/linux/dma/amd_xdma.h diff --git a/MAINTAINERS b/MAINTAINERS index c1be0b2e378a..019d84b2b086 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21691,6 +21691,7 @@ L: dmaengine@vger.kernel.org S: Supported F: drivers/dma/xilinx/xdma-regs.h F: drivers/dma/xilinx/xdma.c +F: include/linux/dma/amd_xdma.h F: include/linux/platform_data/amd_xdma.h XILINX ZYNQMP DPDMA DRIVER diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 35e364a9f9f4..5ad1c1a11f93 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -739,6 +740,7 @@ static int xdma_set_vector_reg(struct xdma_device *xdev, u32 vec_tbl_start, static int xdma_irq_init(struct xdma_device *xdev) { u32 irq = xdev->irq_start; + u32 user_irq_start; int i, j, ret; /* return failure if there are not enough IRQs */ @@ -781,6 +783,18 @@ static int xdma_irq_init(struct xdma_device *xdev) goto failed_init_c2h; } + /* config user IRQ registers if needed */ + user_irq_start = XDMA_CHAN_NUM(xdev); + if (xdev->irq_num > user_irq_start) { + ret = xdma_set_vector_reg(xdev, XDMA_IRQ_USER_VEC_NUM, + user_irq_start, + xdev->irq_num - user_irq_start); + if (ret) { + xdma_err(xdev, "failed to set user vectors: %d", ret); + goto failed_init_c2h; + } + } + /* enable interrupt */ ret = xdma_enable_intr(xdev); if (ret) { @@ -808,6 +822,79 @@ static bool xdma_filter_fn(struct dma_chan *chan, void *param) return chan_info->dir == xdma_chan->dir; } +/** + * xdma_disable_user_irq - Disable user interrupt + * @pdev: Pointer to the platform_device structure + * @irq_num: System IRQ number + */ +void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + u32 user_irq_index; + + user_irq_index = irq_num - xdev->irq_start; + if (user_irq_index < XDMA_CHAN_NUM(xdev) || + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq number"); + return; + } + user_irq_index -= XDMA_CHAN_NUM(xdev); + + xdma_write_reg(xdev, XDMA_IRQ_BASE, XDMA_IRQ_USER_INT_EN_W1C, + (1 << user_irq_index)); +} +EXPORT_SYMBOL(xdma_disable_user_irq); + +/** + * xdma_enable_user_irq - Enable user logic interrupt + * @pdev: Pointer to the platform_device structure + * @irq_num: System IRQ number + */ +int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + u32 user_irq_index; + int ret; + + user_irq_index = irq_num - xdev->irq_start; + if (user_irq_index < XDMA_CHAN_NUM(xdev) || + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq number"); + return -EINVAL; + } + user_irq_index -= XDMA_CHAN_NUM(xdev); + + ret = xdma_write_reg(xdev, XDMA_IRQ_BASE, XDMA_IRQ_USER_INT_EN_W1S, + (1 << user_irq_index)); + if (ret) { + xdma_err(xdev, "set user irq mask failed, %d", ret); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(xdma_enable_user_irq); + +/** + * xdma_get_user_irq - Get system IRQ number + * @pdev: Pointer to the platform_device structure + * @user_irq_index: User logic IRQ wire index + * + * Return: The system IRQ number allocated for the given wire index. + */ +int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + + if (XDMA_CHAN_NUM(xdev) + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq index"); + return -EINVAL; + } + + return xdev->irq_start + XDMA_CHAN_NUM(xdev) + user_irq_index; +} +EXPORT_SYMBOL(xdma_get_user_irq); + /** * xdma_remove - Driver remove function * @pdev: Pointer to the platform_device structure diff --git a/include/linux/dma/amd_xdma.h b/include/linux/dma/amd_xdma.h new file mode 100644 index 000000000000..ceba69ed7cb4 --- /dev/null +++ b/include/linux/dma/amd_xdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _DMAENGINE_AMD_XDMA_H +#define _DMAENGINE_AMD_XDMA_H + +#include +#include + +int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num); +void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num); +int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index); + +#endif /* _DMAENGINE_AMD_XDMA_H */