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Mon, 7 Aug 2023 00:52:14 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 02/10] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Date: Mon, 7 Aug 2023 11:21:41 +0530 Message-ID: <1691387509-2113129-3-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F0:EE_|MW3PR12MB4443:EE_ X-MS-Office365-Filtering-Correlation-Id: 39316a0c-3a24-4e4b-1cc6-08db970a7928 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9dRl2YB/E+Z7m8owhDvMwkwEU1UzBA2489e8gRj4/9VeMfwghRkAUrO5+hUV1f1/g3XyQLHVAGc6iY3/iEpLagDxA+WZ9RkqQOmnOTQk7T0+lqm+0uq53LXLL3iiQuyNT9RYnZM3Ee52bHdUUrzI+AY0ugavXy2BtinQSFsrkgdGt1JvU16PFsWsczgRIiojjioG8lJzFSs/U6v+HYihCQO9M0S6qOkFoeZYYdS6srKmy5H8yI4oWSTBO8nHhjEKIVXgQu5bLruDT8DUleG8FQYYj8BhBXWRh5MGmeWtTWHHWhFydoSAX7/F5+S7qmsEmOXAxvInpEVvkKYzCkeEUIm3KuU4erZtn+NMjvnuFCV9PYnjYtAIIJZEt26DDChpZZfhvtQJl21P3i/gonle1lydfEVf4yyZd5b8WKv62Ew4Cm4erzsL8cr8kf/0TVPYPyHx4uIs01rw3hw5RzegyckE55nMVOSzf4ovUriQtGlX1W8BA+pp9XAabYWO4vS9rl9BfzwDKXLqk2Z/bWUjZHCvWZ1q2Sw13w4GmV/6cLrOnLf6wiNXxbvCak+x1vT21VHRuk0lOrCJHC5icZnWCV8tuxoGNm87i8YBzG5+Zil1QYTwxPlrbdxk6lJpR42GsNfxvsGqcGkE/Fb+0sZeAhP+mxnT7mqmGjJ82uY4ZeLfanPWPk4o2U0IT379Jp3h0pAUvzoDw5DMeAOG5aFV0Uac0l1cC5c4/grZEyg96eyhhzFTCfzvysdyupNFFGlU3ZUsFzTeGNpVzYLXP8PbmB7cxeDwDO7sk4aOvlGZ4NoHA2Lb8IvT3vqc2een6p/F X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(136003)(376002)(39860400002)(82310400008)(451199021)(1800799003)(186006)(46966006)(36840700001)(40470700004)(36860700001)(36756003)(86362001)(83380400001)(81166007)(921005)(356005)(82740400003)(40460700003)(40480700001)(6666004)(966005)(26005)(336012)(41300700001)(316002)(70206006)(4326008)(478600001)(110136005)(54906003)(2906002)(5660300002)(426003)(2616005)(47076005)(7416002)(8936002)(8676002)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 05:52:23.9633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39316a0c-3a24-4e4b-1cc6-08db970a7928 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4443 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt timeout value and causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs. This property is useful when AXI DMA is connected to the streaming IP i.e axiethernet where inter packet latency is critical while still taking the benefit of interrupt coalescing. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Switch to amd.com email address. --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index fea5b09a439d..590d1948f202 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -52,7 +52,9 @@ Optional properties for AXI DMA and MCDMA: Optional properties for AXI DMA: - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. - +- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from + 0-255. Setting this value to zero disables the delay timer interrupt. + 1 timeout interval = 125 * clock period of SG clock. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: