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[v2,4/8] dmaengine: dw: extract dwc_chan_pause() for future use

Message ID 20170102100049.127155-5-andriy.shevchenko@linux.intel.com (mailing list archive)
State Changes Requested
Headers show

Commit Message

Andy Shevchenko Jan. 2, 2017, 10 a.m. UTC 
iDMA 32-bit has a special handling of the FIFO during pause() /
terminate_all(). Prepare code to implement that.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/dw/core.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)
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Patch

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 7f2624f30416..d5283188605e 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -927,22 +927,26 @@  static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 	return 0;
 }
 
-static int dwc_pause(struct dma_chan *chan)
+static void dwc_chan_pause(struct dw_dma_chan *dwc)
 {
-	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-	unsigned long		flags;
 	unsigned int		count = 20;	/* timeout iterations */
 	u32			cfglo;
 
-	spin_lock_irqsave(&dwc->lock, flags);
-
 	cfglo = channel_readl(dwc, CFG_LO);
 	channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 	while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 		udelay(2);
 
 	set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
+}
 
+static int dwc_pause(struct dma_chan *chan)
+{
+	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
+	unsigned long		flags;
+
+	spin_lock_irqsave(&dwc->lock, flags);
+	dwc_chan_pause(dwc);
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
 	return 0;