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Ip=[64.157.242.222]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2178 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Wen He Reviewed-by: Rob Herring --- change in v5: - Replace dts node variable 'queues' to 'fsl,queues' that add vendor prefix change in v4: - Rewrite the bindings document that follows generic DMA bindings file change in v3: - no change change in v2: - Remove indentation - Add "Should be" before 'fsl,ls1021a-qdma' - Replace 'channels' by 'dma-channels' - Replace 'qdma@8390000' by 'dma-controller@8390000' Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 ++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..99b3d74 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,41 @@ +NXP Layerscape SoC qDMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- interrupt-names: Should contain interrupt names: + "qdma-error": the error interrupt + "qdma-queue": the queue interrupt +- fsl,queues: Should contain number of queues supported. + +Optional properties: + +- dma-channels: Number of DMA channels supported by the controller. +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */ + 0x0 0x839a000 0x0 0x2000>; /* Block registers */ + interrupts = , + ; + interrupt-names = "qdma-error", "qdma-queue"; + dma-channels = <8>; + queues = <2>; + big-endian; + }; + +DMA clients must use the format described in dma/dma.txt file.