| Message ID | 20180621115822.20058-2-andrea.merello@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..c894abe28baa 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,7 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be the width of the length register as configured in h/w. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add DOC for it. Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> --- Changes in v2: - change property name - property is now optional - cc DT maintainer --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 1 + 1 file changed, 1 insertion(+)