From patchwork Thu Oct 11 09:46:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Ma X-Patchwork-Id: 10636367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05621112B for ; Thu, 11 Oct 2018 09:51:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1AD628595 for ; Thu, 11 Oct 2018 09:51:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D58142AF61; Thu, 11 Oct 2018 09:51:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7441D28595 for ; Thu, 11 Oct 2018 09:51:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726399AbeJKRR1 (ORCPT ); Thu, 11 Oct 2018 13:17:27 -0400 Received: from inva020.nxp.com ([92.121.34.13]:35676 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726215AbeJKRR1 (ORCPT ); Thu, 11 Oct 2018 13:17:27 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6BB941A019A; Thu, 11 Oct 2018 11:50:53 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9D8B41A0014; Thu, 11 Oct 2018 11:50:47 +0200 (CEST) Received: from titan.ap.freescale.net (TITAN.ap.freescale.net [10.192.208.233]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 483C4402D8; Thu, 11 Oct 2018 17:50:40 +0800 (SGT) From: Peng Ma To: vkoul@kernel.org, leoyang.li@nxp.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, dan.j.williams@intel.com, zw@zh-kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Peng Ma Subject: [PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Thu, 11 Oct 2018 17:46:55 +0800 Message-Id: <20181011094655.45707-7-peng.ma@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181011094655.45707-1-peng.ma@nxp.com> References: <20181011094655.45707-1-peng.ma@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Peng Ma --- Documentation/devicetree/bindings/dma/fsl-qdma.txt | 53 ++++++++++++++++++++ 1 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..7e2160b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,53 @@ +NXP Layerscape SoC qDMA Controller +================================== + +The qDMA supports channel virtualization by allowing DMA jobs to be enqueued into +different command queues. Core can initiate a DMA transaction by preparing a command +descriptor for each DMA job and enqueuing this job to a command queue. + +Required properties: +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg : Specifies base physical address(s) and size of the qDMA registers. + The 1st region is qDMA control register's address and size. + The 2nd region is status queue control register's address and size. + The 3rd region is virtual block control register's address and size. +- interrupts : A list of interrupt-specifiers, one for each entry in + interrupt-names. +- interrupt-names : Should contain: + "qdma-queue0" - the block0 interrupt + "qdma-queue1" - the block1 interrupt + "qdma-queue2" - the block2 interrupt + "qdma-queue3" - the block3 interrupt + "qdma-error" - the error interrupt +- channels : Number of DMA channels supported +- block-number : the virtual block number +- block-offset : the offset of different virtual block +- queues : the number of command queue per virtual block +- status-sizes : status queue size of per virtual block +- queue-sizes : command queue size of per virtual block, the size number based on queues +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + qdma: qdma@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8389000 0x0 0x1000>, /* Status regs */ + <0x0 0x838a000 0x0 0x2000>; /* Block regs */ + interrupts = , + , + ; + interrupt-names = "qdma-error", + "qdma-queue0", "qdma-queue1"; + channels = <8>; + block-number = <2>; + block-offset = <0x1000>; + queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + };