diff mbox series

[1/5] dt-bindings: dma: Document RZ/G2L bindings

Message ID 20210611113642.18457-2-biju.das.jz@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add RZ/G2L DMAC support | expand

Commit Message

Biju Das June 11, 2021, 11:36 a.m. UTC
Document RZ/G2L DMAC bindings.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
 1 file changed, 132 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

Comments

Rob Herring June 11, 2021, 5:55 p.m. UTC | #1
On Fri, 11 Jun 2021 12:36:38 +0100, Biju Das wrote:
> Document RZ/G2L DMAC bindings.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
>  1 file changed, 132 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dts:20:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
   20 |         #include <dt-bindings/clock/r9a07g044-cpg.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1490917

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Rob Herring June 11, 2021, 7:39 p.m. UTC | #2
On Fri, Jun 11, 2021 at 12:36:38PM +0100, Biju Das wrote:
> Document RZ/G2L DMAC bindings.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
>  1 file changed, 132 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> new file mode 100644
> index 000000000000..df54bd6ddfd4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L DMA Controller
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> +      - const: renesas,rz-dmac
> +
> +  reg:
> +    items:
> +      - description: Control and channel register block
> +      - description: DMA extension resource selector block
> +
> +  interrupts:
> +    maxItems: 17
> +
> +  interrupt-names:
> +    maxItems: 17
> +    items:
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"

Is there some reason these need be in undefined order?

> +      - const: error
> +
> +  clocks:
> +    maxItems: 1
> +
> +  '#dma-cells':
> +    const: 1
> +    description:
> +      The cell specifies the MID/RID of the DMAC port connected to
> +      the DMA client.
> +
> +  dma-channels:
> +    const: 16
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  renesas,rz-dmac-slavecfg:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: |
> +      DMA configuration for a slave channel. Each channel must have an array of
> +      3 items as below.
> +      first item in the array is MID+RID
> +      second item in the array is slave src or dst address
> +      third item in the array is channel configuration value.

Why not put all these in the dma-cells? You already have 1 of them.

Though doesn't the client device know what address to use?

> +    items:
> +      minItems: 3
> +      maxItems: 48
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - '#dma-cells'
> +  - dma-channels
> +  - power-domains
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +    dmac: dma-controller@11820000 {
> +        compatible = "renesas,dmac-r9a07g044",
> +                     "renesas,rz-dmac";
> +        reg = <0x11820000 0x10000>,
> +              <0x11830000 0x10000>;
> +        interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> +        interrupt-names = "ch0", "ch1", "ch2", "ch3",
> +                          "ch4", "ch5", "ch6", "ch7",
> +                          "ch8", "ch9", "ch10", "ch11",
> +                          "ch12", "ch13", "ch14", "ch15",
> +                          "error";
> +        clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A07G044_CLK_DMAC>;
> +        #dma-cells = <1>;
> +        dma-channels = <16>;
> +        renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
> +    };
> -- 
> 2.17.1
Biju Das June 12, 2021, 12:17 p.m. UTC | #3
Hi Rob,

Thanks for the review.

> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> On Fri, 11 Jun 2021 12:36:38 +0100, Biju Das wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
> >  1 file changed, 132 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> >
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dts:20:18:
> fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
>    20 |         #include <dt-bindings/clock/r9a07g044-cpg.h>
>       |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:380:
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dt.yaml]
> Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1416: dt_binding_check] Error 2 \ndoc reference errors
> (make refcheckdocs):
> 
> See
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fpatch%2F1490917&amp;data=04%7C01%7Cbiju.das.jz%40bp.renesas
> .com%7C0b0cf26acc004dba607508d92d0222fe%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C637590309476730777%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=lZ%2F0v9D4
> 9djAW8E4sA3zcHOFs4x%2F073f40FkAGZJ0ZI%3D&amp;reserved=0
> 
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.

Sorry, The dependency patch is just queued. Next time, I will make sure
dependency patch is in the most recent rc1 before posting.

> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit.

Sure will check and re-submit.

Regards,
Biju
Biju Das June 12, 2021, 12:26 p.m. UTC | #4
Hi Rob,

Thanks for the feedback.

> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> On Fri, Jun 11, 2021 at 12:36:38PM +0100, Biju Das wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
> >  1 file changed, 132 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > new file mode 100644
> > index 000000000000..df54bd6ddfd4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=04%7C
> > +01%7Cbiju.das.jz%40bp.renesas.com%7Ce46660b298b942937fe408d92d109c19%
> > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637590371623792000%7CUnk
> > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=kirztzPuCmsjeKEivOgQZqP5obsByrSaTnQ
> > +bzQbU%2BRM%3D&amp;reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7Ce46660b298b942937fe408d92d109c19%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637590371623792000%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&amp;sdata=U2lrBvVVhySXVYHK6Qk41VTGijep8yPaTCMJpSjRsXs%3D&am
> > +p;reserved=0
> > +
> > +title: Renesas RZ/G2L DMA Controller
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +allOf:
> > +  - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > +      - const: renesas,rz-dmac
> > +
> > +  reg:
> > +    items:
> > +      - description: Control and channel register block
> > +      - description: DMA extension resource selector block
> > +
> > +  interrupts:
> > +    maxItems: 17
> > +
> > +  interrupt-names:
> > +    maxItems: 17
> > +    items:
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> > +      - pattern: "^ch([0-9]|1[0-5])$"
> 
> Is there some reason these need be in undefined order?
No. I will make it as defined order in next version.

> 
> > +      - const: error
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  '#dma-cells':
> > +    const: 1
> > +    description:
> > +      The cell specifies the MID/RID of the DMAC port connected to
> > +      the DMA client.
> > +
> > +  dma-channels:
> > +    const: 16
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +  renesas,rz-dmac-slavecfg:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > +    description: |
> > +      DMA configuration for a slave channel. Each channel must have an
> array of
> > +      3 items as below.
> > +      first item in the array is MID+RID
> > +      second item in the array is slave src or dst address
> > +      third item in the array is channel configuration value.
> 
> Why not put all these in the dma-cells? You already have 1 of them.

Thanks for the suggestion. I will make use of dma-cells and will remove the above property
in next revision. Basically It simplifies the implementation as well.

> Though doesn't the client device know what address to use?
Indeed. it knows.

Cheers,
Biju
> 
> > +    items:
> > +      minItems: 3
> > +      maxItems: 48
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - interrupt-names
> > +  - clocks
> > +  - '#dma-cells'
> > +  - dma-channels
> > +  - power-domains
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > +    dmac: dma-controller@11820000 {
> > +        compatible = "renesas,dmac-r9a07g044",
> > +                     "renesas,rz-dmac";
> > +        reg = <0x11820000 0x10000>,
> > +              <0x11830000 0x10000>;
> > +        interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> > +        interrupt-names = "ch0", "ch1", "ch2", "ch3",
> > +                          "ch4", "ch5", "ch6", "ch7",
> > +                          "ch8", "ch9", "ch10", "ch11",
> > +                          "ch12", "ch13", "ch14", "ch15",
> > +                          "error";
> > +        clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
> > +        power-domains = <&cpg>;
> > +        resets = <&cpg R9A07G044_CLK_DMAC>;
> > +        #dma-cells = <1>;
> > +        dma-channels = <16>;
> > +        renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
> > +    };
> > --
> > 2.17.1
Geert Uytterhoeven June 14, 2021, 12:11 p.m. UTC | #5
Hi Biju,

On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document RZ/G2L DMAC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L DMA Controller
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}

Please use "renesas,r9a07g044-dmac".

> +      - const: renesas,rz-dmac

Does this need many changes for RZ/A1H and RZ/A2M?

> +  renesas,rz-dmac-slavecfg:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: |
> +      DMA configuration for a slave channel. Each channel must have an array of
> +      3 items as below.
> +      first item in the array is MID+RID

Already in dmas.

> +      second item in the array is slave src or dst address

As pointed out by Rob, already known by the slave driver.

> +      third item in the array is channel configuration value.

What exactly is this?
Does the R-Car DMAC have this too? If yes, how does its driver handle it?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das June 14, 2021, 12:54 p.m. UTC | #6
Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> Hi Biju,
> 
> On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=04%7C
> > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%
> > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnk
> > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDejp8wo
> > +Nrx9iO0ht8%3D&amp;reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw%3D&
> > +amp;reserved=0
> > +
> > +title: Renesas RZ/G2L DMA Controller
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +allOf:
> > +  - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> 
> Please use "renesas,r9a07g044-dmac".

OK. Will change.

> > +      - const: renesas,rz-dmac
> 
> Does this need many changes for RZ/A1H and RZ/A2M?

It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
There is some difference in MID bit size. Other wise both identical.

 
> > +  renesas,rz-dmac-slavecfg:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > +    description: |
> > +      DMA configuration for a slave channel. Each channel must have an
> array of
> > +      3 items as below.
> > +      first item in the array is MID+RID
> 
> Already in dmas.
> 
> > +      second item in the array is slave src or dst address
> 
> As pointed out by Rob, already known by the slave driver.
> 
> > +      third item in the array is channel configuration value.
> 
> What exactly is this?
> Does the R-Car DMAC have this too? If yes, how does its driver handle it?

On R-CAR DMAC, we have only MID + RID values. Where as here we have channel configuration value With different set of parameter as mentioned in Table 16.4.

Please see Page 569, Table 16.4 On-Chip Module requests section. 

For eg:- as per Rob's suggestion, I have modelled the driver with the below entries in ALSA driver for playback/record use case.

dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
       <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
dma-names = "tx", "rx";

Using first parameter, it gets dmac channel. using second and third parameter it configures 
the channel.

Regards,
Biju

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds
Laurent Pinchart June 14, 2021, 2:29 p.m. UTC | #7
On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > -----Original Message-----
> > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> > 
> > Hi Biju,
> > 
> > On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Document RZ/G2L DMAC bindings.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > 
> > Thanks for your patch!
> > 
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > @@ -0,0 +1,132 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=04%7C
> > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%
> > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnk
> > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDejp8wo
> > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > +$schema:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571da19
> > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWFpbGZ
> > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw%3D&
> > > +amp;reserved=0

*sigh*

> > > +
> > > +title: Renesas RZ/G2L DMA Controller
> > > +
> > > +maintainers:
> > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +allOf:
> > > +  - $ref: "dma-controller.yaml#"
> > > +
> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > 
> > Please use "renesas,r9a07g044-dmac".
> 
> OK. Will change.
> 
> > > +      - const: renesas,rz-dmac
> > 
> > Does this need many changes for RZ/A1H and RZ/A2M?
> 
> It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> There is some difference in MID bit size. Other wise both identical.
> 
>  
> > > +  renesas,rz-dmac-slavecfg:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > +    description: |
> > > +      DMA configuration for a slave channel. Each channel must have an
> > array of
> > > +      3 items as below.
> > > +      first item in the array is MID+RID
> > 
> > Already in dmas.
> > 
> > > +      second item in the array is slave src or dst address
> > 
> > As pointed out by Rob, already known by the slave driver.
> > 
> > > +      third item in the array is channel configuration value.
> > 
> > What exactly is this?

What would prevent the DMA client from passing the configuration to the
DMA channel through the DMA engine API, just like it passes the slave
source or destination address ?

> > Does the R-Car DMAC have this too? If yes, how does its driver handle it?
> 
> On R-CAR DMAC, we have only MID + RID values. Where as here we have channel configuration value With different set of parameter as mentioned in Table 16.4.
> 
> Please see Page 569, Table 16.4 On-Chip Module requests section. 
> 
> For eg:- as per Rob's suggestion, I have modelled the driver with the below entries in ALSA driver for playback/record use case.
> 
> dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
>        <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> dma-names = "tx", "rx";
> 
> Using first parameter, it gets dmac channel. using second and third parameter it configures 
> the channel.
Biju Das June 14, 2021, 4:09 p.m. UTC | #8
Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > -----Original Message-----
> > > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> > >
> > > Hi Biju,
> > >
> > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > Document RZ/G2L DMAC bindings.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > @@ -0,0 +1,132 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=0
> > > > +4%7C
> > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da
> > > > +0c0%
> > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7
> > > > +CUnk
> > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > > +1haW
> > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDej
> > > > +p8wo
> > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > +$schema:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571
> > > > +da19
> > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWF
> > > > +pbGZ
> > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > +Mn0%
> > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw
> > > > +%3D&
> > > > +amp;reserved=0
> 
> *sigh*
> 
> > > > +
> > > > +title: Renesas RZ/G2L DMA Controller
> > > > +
> > > > +maintainers:
> > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +allOf:
> > > > +  - $ref: "dma-controller.yaml#"
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    items:
> > > > +      - enum:
> > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > >
> > > Please use "renesas,r9a07g044-dmac".
> >
> > OK. Will change.
> >
> > > > +      - const: renesas,rz-dmac
> > >
> > > Does this need many changes for RZ/A1H and RZ/A2M?
> >
> > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't
> have the board.
> > There is some difference in MID bit size. Other wise both identical.
> >
> >
> > > > +  renesas,rz-dmac-slavecfg:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > +    description: |
> > > > +      DMA configuration for a slave channel. Each channel must
> > > > + have an
> > > array of
> > > > +      3 items as below.
> > > > +      first item in the array is MID+RID
> > >
> > > Already in dmas.
> > >
> > > > +      second item in the array is slave src or dst address
> > >
> > > As pointed out by Rob, already known by the slave driver.
> > >
> > > > +      third item in the array is channel configuration value.
> > >
> > > What exactly is this?
> 
> What would prevent the DMA client from passing the configuration to the
> DMA channel through the DMA engine API, just like it passes the slave
> source or destination address ?

On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx. 
The only way we can distinguish it is from channel configuration value.

Cheers,
Biju


> 
> > > Does the R-Car DMAC have this too? If yes, how does its driver handle
> it?
> >
> > On R-CAR DMAC, we have only MID + RID values. Where as here we have
> channel configuration value With different set of parameter as mentioned
> in Table 16.4.
> >
> > Please see Page 569, Table 16.4 On-Chip Module requests section.
> >
> > For eg:- as per Rob's suggestion, I have modelled the driver with the
> below entries in ALSA driver for playback/record use case.
> >
> > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> >        <&dmac 0x256 0x10049c1c
> > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > dma-names = "tx", "rx";
> >
> > Using first parameter, it gets dmac channel. using second and third
> > parameter it configures the channel.
> 
> --
> Regards,
> 
> Laurent Pinchart
Laurent Pinchart June 14, 2021, 4:17 p.m. UTC | #9
Hi Biju,

On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > Document RZ/G2L DMAC bindings.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > > @@ -0,0 +1,132 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > > +devi
> > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=0
> > > > > +4%7C
> > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da
> > > > > +0c0%
> > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7
> > > > > +CUnk
> > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > > > +1haW
> > > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDej
> > > > > +p8wo
> > > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > > +$schema:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > > +devi
> > > > > +cetree.org%2Fmeta-
> > schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571
> > > > > +da19
> > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWF
> > > > > +pbGZ
> > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > > +Mn0%
> > > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw
> > > > > +%3D&
> > > > > +amp;reserved=0
> > 
> > *sigh*
> > 
> > > > > +
> > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > +
> > > > > +maintainers:
> > > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > +
> > > > > +allOf:
> > > > > +  - $ref: "dma-controller.yaml#"
> > > > > +
> > > > > +properties:
> > > > > +  compatible:
> > > > > +    items:
> > > > > +      - enum:
> > > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > > >
> > > > Please use "renesas,r9a07g044-dmac".
> > >
> > > OK. Will change.
> > >
> > > > > +      - const: renesas,rz-dmac
> > > >
> > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > >
> > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > There is some difference in MID bit size. Other wise both identical.
> > >
> > > > > +  renesas,rz-dmac-slavecfg:
> > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > +    description: |
> > > > > +      DMA configuration for a slave channel. Each channel must
> > > > > + have an array of
> > > > > +      3 items as below.
> > > > > +      first item in the array is MID+RID
> > > >
> > > > Already in dmas.
> > > >
> > > > > +      second item in the array is slave src or dst address
> > > >
> > > > As pointed out by Rob, already known by the slave driver.
> > > >
> > > > > +      third item in the array is channel configuration value.
> > > >
> > > > What exactly is this?
> > 
> > What would prevent the DMA client from passing the configuration to the
> > DMA channel through the DMA engine API, just like it passes the slave
> > source or destination address ?
> 
> On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx. 
> The only way we can distinguish it is from channel configuration value.

Are those two different hardware DMA channels ? And configuration values
change between the two ?

> > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > handle it?
> > >
> > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > have channel configuration value With different set of parameter
> > > as mentioned in Table 16.4.
> > >
> > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > >
> > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > the below entries in ALSA driver for playback/record use case.
> > >
> > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > >        <&dmac 0x256 0x10049c1c
> > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > dma-names = "tx", "rx";
> > >
> > > Using first parameter, it gets dmac channel. using second and third
> > > parameter it configures the channel.
Biju Das June 14, 2021, 4:24 p.m. UTC | #10
Hi Laurent,

> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> Hi Biju,
> 
> On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > Document RZ/G2L DMAC bindings.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > Reviewed-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.ya
> > > > > > +++ ml
> > > > > > @@ -0,0 +1,132 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML
> > > > > > +1.2
> > > > > > +---
> > > > > > +$id:
> > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > +F%2F
> > > > > > +devi
> > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;da
> > > > > > +ta=0
> > > > > > +4%7C
> > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92
> > > > > > +f2da
> > > > > > +0c0%
> > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6375926952868468
> > > > > > +09%7
> > > > > > +CUnk
> > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
> > > > > > +I6Ik
> > > > > > +1haW
> > > > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtz
> > > > > > +uDej
> > > > > > +p8wo
> > > > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > > > +$schema:
> > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > +F%2F
> > > > > > +devi
> > > > > > +cetree.org%2Fmeta-
> > > schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d8
> > > > > > +2571
> > > > > > +da19
> > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7
> > > > > > +CTWF
> > > > > > +pbGZ
> > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> > > > > > +VCI6
> > > > > > +Mn0%
> > > > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnh
> > > > > > +Jraw
> > > > > > +%3D&
> > > > > > +amp;reserved=0
> > >
> > > *sigh*
> > >
> > > > > > +
> > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > +
> > > > > > +maintainers:
> > > > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > +
> > > > > > +allOf:
> > > > > > +  - $ref: "dma-controller.yaml#"
> > > > > > +
> > > > > > +properties:
> > > > > > +  compatible:
> > > > > > +    items:
> > > > > > +      - enum:
> > > > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > > > >
> > > > > Please use "renesas,r9a07g044-dmac".
> > > >
> > > > OK. Will change.
> > > >
> > > > > > +      - const: renesas,rz-dmac
> > > > >
> > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > >
> > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I
> don't have the board.
> > > > There is some difference in MID bit size. Other wise both identical.
> > > >
> > > > > > +  renesas,rz-dmac-slavecfg:
> > > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > +    description: |
> > > > > > +      DMA configuration for a slave channel. Each channel
> > > > > > + must have an array of
> > > > > > +      3 items as below.
> > > > > > +      first item in the array is MID+RID
> > > > >
> > > > > Already in dmas.
> > > > >
> > > > > > +      second item in the array is slave src or dst address
> > > > >
> > > > > As pointed out by Rob, already known by the slave driver.
> > > > >
> > > > > > +      third item in the array is channel configuration value.
> > > > >
> > > > > What exactly is this?
> > >
> > > What would prevent the DMA client from passing the configuration to
> > > the DMA channel through the DMA engine API, just like it passes the
> > > slave source or destination address ?
> >
> > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx
> and rx.
> > The only way we can distinguish it is from channel configuration value.
> 
> Are those two different hardware DMA channels ? And configuration values
> change between the two ?

Yes, REQD is different, apart from this Rx have transfer source and Tx have Transfer destination.
This particular SSIF ch2 is used only for half duplex compared to other SSIF channels.

Regards,
Biju

> 
> > > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > > handle it?
> > > >
> > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > have channel configuration value With different set of parameter
> > > > as mentioned in Table 16.4.
> > > >
> > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > >
> > > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > > the below entries in ALSA driver for playback/record use case.
> > > >
> > > > dmas = <&dmac 0x255 0x10049c18
> CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > >        <&dmac 0x256 0x10049c1c
> > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > dma-names = "tx", "rx";
> > > >
> > > > Using first parameter, it gets dmac channel. using second and
> > > > third parameter it configures the channel.
> 
> --
> Regards,
> 
> Laurent Pinchart
Laurent Pinchart June 14, 2021, 4:28 p.m. UTC | #11
Hi Biju,

On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > >
> > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > Reviewed-by: Lad Prabhakar
> > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.ya
> > > > > > > +++ ml
> > > > > > > @@ -0,0 +1,132 @@
> > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > +%YAML
> > > > > > > +1.2
> > > > > > > +---
> > > > > > > +$id:
> > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > > +F%2F
> > > > > > > +devi
> > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;da
> > > > > > > +ta=0
> > > > > > > +4%7C
> > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92
> > > > > > > +f2da
> > > > > > > +0c0%
> > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6375926952868468
> > > > > > > +09%7
> > > > > > > +CUnk
> > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
> > > > > > > +I6Ik
> > > > > > > +1haW
> > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtz
> > > > > > > +uDej
> > > > > > > +p8wo
> > > > > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > > > > +$schema:
> > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > > +F%2F
> > > > > > > +devi
> > > > > > > +cetree.org%2Fmeta-
> > > > schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d8
> > > > > > > +2571
> > > > > > > +da19
> > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7
> > > > > > > +CTWF
> > > > > > > +pbGZ
> > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> > > > > > > +VCI6
> > > > > > > +Mn0%
> > > > > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnh
> > > > > > > +Jraw
> > > > > > > +%3D&
> > > > > > > +amp;reserved=0
> > > >
> > > > *sigh*
> > > >
> > > > > > > +
> > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > +
> > > > > > > +maintainers:
> > > > > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > +
> > > > > > > +allOf:
> > > > > > > +  - $ref: "dma-controller.yaml#"
> > > > > > > +
> > > > > > > +properties:
> > > > > > > +  compatible:
> > > > > > > +    items:
> > > > > > > +      - enum:
> > > > > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > > > > >
> > > > > > Please use "renesas,r9a07g044-dmac".
> > > > >
> > > > > OK. Will change.
> > > > >
> > > > > > > +      - const: renesas,rz-dmac
> > > > > >
> > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > >
> > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > > > There is some difference in MID bit size. Other wise both identical.
> > > > >
> > > > > > > +  renesas,rz-dmac-slavecfg:
> > > > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > +    description: |
> > > > > > > +      DMA configuration for a slave channel. Each channel
> > > > > > > + must have an array of
> > > > > > > +      3 items as below.
> > > > > > > +      first item in the array is MID+RID
> > > > > >
> > > > > > Already in dmas.
> > > > > >
> > > > > > > +      second item in the array is slave src or dst address
> > > > > >
> > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > >
> > > > > > > +      third item in the array is channel configuration value.
> > > > > >
> > > > > > What exactly is this?
> > > >
> > > > What would prevent the DMA client from passing the configuration to
> > > > the DMA channel through the DMA engine API, just like it passes the
> > > > slave source or destination address ?
> > >
> > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
> > > The only way we can distinguish it is from channel configuration value.
> > 
> > Are those two different hardware DMA channels ? And configuration values
> > change between the two ?
> 
> Yes, REQD is different, apart from this Rx have transfer source and Tx have Transfer destination.
> This particular SSIF ch2 is used only for half duplex compared to other SSIF channels.

Does this mean there's a single DMA channel, used by two clients, but
not at the same time as it only supports half-duplex ?

> > > > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > > > handle it?
> > > > >
> > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > have channel configuration value With different set of parameter
> > > > > as mentioned in Table 16.4.
> > > > >
> > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > >
> > > > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > > > the below entries in ALSA driver for playback/record use case.
> > > > >
> > > > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > >        <&dmac 0x256 0x10049c1c
> > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > dma-names = "tx", "rx";
> > > > >
> > > > > Using first parameter, it gets dmac channel. using second and
> > > > > third parameter it configures the channel.
Biju Das June 14, 2021, 4:33 p.m. UTC | #12
Hi Laurent,

> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> 
> Hi Biju,
> 
> On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > > >
> > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > Reviewed-by: Lad Prabhakar
> > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Thanks for your patch!
> > > > > > >
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dma
> > > > > > > > +++ c.ya
> > > > > > > > +++ ml
> > > > > > > > @@ -0,0 +1,132 @@
> > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > +%YAML
> > > > > > > > +1.2
> > > > > > > > +---
> > > > > > > > +$id:
> > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > +3A%2
> > > > > > > > +F%2F
> > > > > > > > +devi
> > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&am
> > > > > > > > +p;da
> > > > > > > > +ta=0
> > > > > > > > +4%7C
> > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d850
> > > > > > > > +8d92
> > > > > > > > +f2da
> > > > > > > > +0c0%
> > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286
> > > > > > > > +8468
> > > > > > > > +09%7
> > > > > > > > +CUnk
> > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > > > > > > > +JBTi
> > > > > > > > +I6Ik
> > > > > > > > +1haW
> > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCc
> > > > > > > > +rNtz
> > > > > > > > +uDej
> > > > > > > > +p8wo
> > > > > > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > > > > > +$schema:
> > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > +3A%2
> > > > > > > > +F%2F
> > > > > > > > +devi
> > > > > > > > +cetree.org%2Fmeta-
> > > > > schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C
> > > > > > > > +53d8
> > > > > > > > +2571
> > > > > > > > +da19
> > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnkno
> > > > > > > > +wn%7
> > > > > > > > +CTWF
> > > > > > > > +pbGZ
> > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > > > > > > > +LCJX
> > > > > > > > +VCI6
> > > > > > > > +Mn0%
> > > > > > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIA
> > > > > > > > +dLnh
> > > > > > > > +Jraw
> > > > > > > > +%3D&
> > > > > > > > +amp;reserved=0
> > > > >
> > > > > *sigh*
> > > > >
> > > > > > > > +
> > > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > > +
> > > > > > > > +maintainers:
> > > > > > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > +
> > > > > > > > +allOf:
> > > > > > > > +  - $ref: "dma-controller.yaml#"
> > > > > > > > +
> > > > > > > > +properties:
> > > > > > > > +  compatible:
> > > > > > > > +    items:
> > > > > > > > +      - enum:
> > > > > > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > > > > > >
> > > > > > > Please use "renesas,r9a07g044-dmac".
> > > > > >
> > > > > > OK. Will change.
> > > > > >
> > > > > > > > +      - const: renesas,rz-dmac
> > > > > > >
> > > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > > >
> > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since
> I don't have the board.
> > > > > > There is some difference in MID bit size. Other wise both
> identical.
> > > > > >
> > > > > > > > +  renesas,rz-dmac-slavecfg:
> > > > > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > > +    description: |
> > > > > > > > +      DMA configuration for a slave channel. Each channel
> > > > > > > > + must have an array of
> > > > > > > > +      3 items as below.
> > > > > > > > +      first item in the array is MID+RID
> > > > > > >
> > > > > > > Already in dmas.
> > > > > > >
> > > > > > > > +      second item in the array is slave src or dst
> > > > > > > > + address
> > > > > > >
> > > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > > >
> > > > > > > > +      third item in the array is channel configuration
> value.
> > > > > > >
> > > > > > > What exactly is this?
> > > > >
> > > > > What would prevent the DMA client from passing the configuration
> > > > > to the DMA channel through the DMA engine API, just like it
> > > > > passes the slave source or destination address ?
> > > >
> > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both
> tx and rx.
> > > > The only way we can distinguish it is from channel configuration
> value.
> > >
> > > Are those two different hardware DMA channels ? And configuration
> > > values change between the two ?
> >
> > Yes, REQD is different, apart from this Rx have transfer source and Tx
> have Transfer destination.
> > This particular SSIF ch2 is used only for half duplex compared to other
> SSIF channels.
> 
> Does this mean there's a single DMA channel, used by two clients, but not
> at the same time as it only supports half-duplex ?


From hardware perspective, it is 2 channel. For eg:- playback/recording use case.
You cannot do simultaneous playback, but you can do playback or record separately.

Cheers,
Biju

> > > > > > > Does the R-Car DMAC have this too? If yes, how does its
> > > > > > > driver handle it?
> > > > > >
> > > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > > have channel configuration value With different set of
> > > > > > parameter as mentioned in Table 16.4.
> > > > > >
> > > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > > >
> > > > > > For eg:- as per Rob's suggestion, I have modelled the driver
> > > > > > with the below entries in ALSA driver for playback/record use
> case.
> > > > > >
> > > > > > dmas = <&dmac 0x255 0x10049c18
> CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > >        <&dmac 0x256 0x10049c1c
> > > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > > dma-names = "tx", "rx";
> > > > > >
> > > > > > Using first parameter, it gets dmac channel. using second and
> > > > > > third parameter it configures the channel.
> 
> --
> Regards,
> 
> Laurent Pinchart
Laurent Pinchart June 14, 2021, 5:30 p.m. UTC | #13
Hi Biju,

On Mon, Jun 14, 2021 at 04:33:03PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > >
> > > > > > > > Thanks for your patch!
> > > > > > > >
> > > > > > > > > --- /dev/null
> > > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dma
> > > > > > > > > +++ c.ya
> > > > > > > > > +++ ml
> > > > > > > > > @@ -0,0 +1,132 @@
> > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > > +%YAML
> > > > > > > > > +1.2
> > > > > > > > > +---
> > > > > > > > > +$id:
> > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > > +3A%2
> > > > > > > > > +F%2F
> > > > > > > > > +devi
> > > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&am
> > > > > > > > > +p;da
> > > > > > > > > +ta=0
> > > > > > > > > +4%7C
> > > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d850
> > > > > > > > > +8d92
> > > > > > > > > +f2da
> > > > > > > > > +0c0%
> > > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286
> > > > > > > > > +8468
> > > > > > > > > +09%7
> > > > > > > > > +CUnk
> > > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > > > > > > > > +JBTi
> > > > > > > > > +I6Ik
> > > > > > > > > +1haW
> > > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=5Jh%2FxPaia5ZOY0CrViQCc
> > > > > > > > > +rNtz
> > > > > > > > > +uDej
> > > > > > > > > +p8wo
> > > > > > > > > +Nrx9iO0ht8%3D&amp;reserved=0
> > > > > > > > > +$schema:
> > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > > +3A%2
> > > > > > > > > +F%2F
> > > > > > > > > +devi
> > > > > > > > > +cetree.org%2Fmeta-
> > > > > > schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C
> > > > > > > > > +53d8
> > > > > > > > > +2571
> > > > > > > > > +da19
> > > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnkno
> > > > > > > > > +wn%7
> > > > > > > > > +CTWF
> > > > > > > > > +pbGZ
> > > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > > > > > > > > +LCJX
> > > > > > > > > +VCI6
> > > > > > > > > +Mn0%
> > > > > > > > > +3D%7C1000&amp;sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIA
> > > > > > > > > +dLnh
> > > > > > > > > +Jraw
> > > > > > > > > +%3D&
> > > > > > > > > +amp;reserved=0
> > > > > >
> > > > > > *sigh*
> > > > > >
> > > > > > > > > +
> > > > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > > > +
> > > > > > > > > +maintainers:
> > > > > > > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > +
> > > > > > > > > +allOf:
> > > > > > > > > +  - $ref: "dma-controller.yaml#"
> > > > > > > > > +
> > > > > > > > > +properties:
> > > > > > > > > +  compatible:
> > > > > > > > > +    items:
> > > > > > > > > +      - enum:
> > > > > > > > > +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> > > > > > > >
> > > > > > > > Please use "renesas,r9a07g044-dmac".
> > > > > > >
> > > > > > > OK. Will change.
> > > > > > >
> > > > > > > > > +      - const: renesas,rz-dmac
> > > > > > > >
> > > > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > > > >
> > > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > > > > > There is some difference in MID bit size. Other wise both identical.
> > > > > > >
> > > > > > > > > +  renesas,rz-dmac-slavecfg:
> > > > > > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > > > +    description: |
> > > > > > > > > +      DMA configuration for a slave channel. Each channel
> > > > > > > > > + must have an array of
> > > > > > > > > +      3 items as below.
> > > > > > > > > +      first item in the array is MID+RID
> > > > > > > >
> > > > > > > > Already in dmas.
> > > > > > > >
> > > > > > > > > +      second item in the array is slave src or dst
> > > > > > > > > + address
> > > > > > > >
> > > > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > > > >
> > > > > > > > > +      third item in the array is channel configuration value.
> > > > > > > >
> > > > > > > > What exactly is this?
> > > > > >
> > > > > > What would prevent the DMA client from passing the configuration
> > > > > > to the DMA channel through the DMA engine API, just like it
> > > > > > passes the slave source or destination address ?
> > > > >
> > > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
> > > > > The only way we can distinguish it is from channel configuration value.
> > > >
> > > > Are those two different hardware DMA channels ? And configuration
> > > > values change between the two ?
> > >
> > > Yes, REQD is different, apart from this Rx have transfer source and Tx
> > > have Transfer destination.
> > > This particular SSIF ch2 is used only for half duplex compared to other
> > > SSIF channels.
> > 
> > Does this mean there's a single DMA channel, used by two clients, but not
> > at the same time as it only supports half-duplex ?
> 
> From hardware perspective, it is 2 channel. For eg:- playback/recording use case.
> You cannot do simultaneous playback, but you can do playback or record separately.

If the two channels have the same MID+RID and only differ by the
direction, I'd add a cell in the dmas property with the direction only.
The source/destination address should be dropped, as it's already known
by the driver.

This being said, in your example below, you have

dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
       <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
dma-names = "tx", "rx";

This looks like different MID+RID values for the two channels.

> > > > > > > > Does the R-Car DMAC have this too? If yes, how does its
> > > > > > > > driver handle it?
> > > > > > >
> > > > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > > > have channel configuration value With different set of
> > > > > > > parameter as mentioned in Table 16.4.
> > > > > > >
> > > > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > > > >
> > > > > > > For eg:- as per Rob's suggestion, I have modelled the driver
> > > > > > > with the below entries in ALSA driver for playback/record use case.
> > > > > > >
> > > > > > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > > >        <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > > > dma-names = "tx", "rx";
> > > > > > >
> > > > > > > Using first parameter, it gets dmac channel. using second and
> > > > > > > third parameter it configures the channel.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
new file mode 100644
index 000000000000..df54bd6ddfd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -0,0 +1,132 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L DMA Controller
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
+      - const: renesas,rz-dmac
+
+  reg:
+    items:
+      - description: Control and channel register block
+      - description: DMA extension resource selector block
+
+  interrupts:
+    maxItems: 17
+
+  interrupt-names:
+    maxItems: 17
+    items:
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - pattern: "^ch([0-9]|1[0-5])$"
+      - const: error
+
+  clocks:
+    maxItems: 1
+
+  '#dma-cells':
+    const: 1
+    description:
+      The cell specifies the MID/RID of the DMAC port connected to
+      the DMA client.
+
+  dma-channels:
+    const: 16
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  renesas,rz-dmac-slavecfg:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      DMA configuration for a slave channel. Each channel must have an array of
+      3 items as below.
+      first item in the array is MID+RID
+      second item in the array is slave src or dst address
+      third item in the array is channel configuration value.
+    items:
+      minItems: 3
+      maxItems: 48
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - '#dma-cells'
+  - dma-channels
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    dmac: dma-controller@11820000 {
+        compatible = "renesas,dmac-r9a07g044",
+                     "renesas,rz-dmac";
+        reg = <0x11820000 0x10000>,
+              <0x11830000 0x10000>;
+        interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                          "ch4", "ch5", "ch6", "ch7",
+                          "ch8", "ch9", "ch10", "ch11",
+                          "ch12", "ch13", "ch14", "ch15",
+                          "error";
+        clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A07G044_CLK_DMAC>;
+        #dma-cells = <1>;
+        dma-channels = <16>;
+        renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
+    };