From patchwork Wed Sep 22 11:04:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12510285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F36EC433EF for ; Wed, 22 Sep 2021 11:17:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2200B6054E for ; Wed, 22 Sep 2021 11:17:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235382AbhIVLSq (ORCPT ); Wed, 22 Sep 2021 07:18:46 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:54362 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235701AbhIVLSh (ORCPT ); Wed, 22 Sep 2021 07:18:37 -0400 X-IronPort-AV: E=Sophos;i="5.85,313,1624287600"; d="scan'208";a="94818589" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 22 Sep 2021 20:17:05 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A83074004D08; Wed, 22 Sep 2021 20:17:03 +0900 (JST) From: Biju Das To: Vinod Koul Cc: Biju Das , Lad Prabhakar , dmaengine@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH] dmaengine: sh: rz-dmac: Add DMA clock handling Date: Wed, 22 Sep 2021 12:04:53 +0100 Message-Id: <20210922110453.25122-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Currently, DMA clocks are turned on by the bootloader. This patch adds support for DMA clock handling so that the driver manages the DMA clocks. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/dma/sh/rz-dmac.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index f9f30cbeccbe..52a1419370d7 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -872,6 +873,9 @@ static int rz_dmac_probe(struct platform_device *pdev) /* Initialize the channels. */ INIT_LIST_HEAD(&dmac->engine.channels); + pm_runtime_enable(&pdev->dev); + pm_runtime_resume_and_get(&pdev->dev); + for (i = 0; i < dmac->n_channels; i++) { ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i); if (ret < 0) @@ -925,6 +929,9 @@ static int rz_dmac_probe(struct platform_device *pdev) channel->lmdesc.base_dma); } + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return ret; } @@ -943,6 +950,8 @@ static int rz_dmac_remove(struct platform_device *pdev) } of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&dmac->engine); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); return 0; }