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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2022 13:22:55.3049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbab01ec-103b-4ef5-d8ed-08da22d0e142 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4223 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Initialize slave_bw and remove unused switch case in get_transfer_param() Fixes: ee17028009d4 ("dmaengine: tegra: Add tegra gpcdma driver") Reported-by: Dan Carpenter Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index f12327732041..6b8d34165176 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -830,10 +830,6 @@ static int get_transfer_param(struct tegra_dma_channel *tdc, *slave_bw = tdc->dma_sconfig.src_addr_width; *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC; return 0; - case DMA_MEM_TO_MEM: - *burst_size = tdc->dma_sconfig.src_addr_width; - *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM; - return 0; default: dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); } @@ -985,8 +981,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl, { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; + enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED; u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0; - enum dma_slave_buswidth slave_bw; struct tegra_dma_sg_req *sg_req; struct tegra_dma_desc *dma_desc; struct scatterlist *sg; @@ -1103,12 +1099,12 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l size_t period_len, enum dma_transfer_direction direction, unsigned long flags) { + enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED; + u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size; + unsigned int max_dma_count, len, period_count, i; struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sg_req; - enum dma_slave_buswidth slave_bw; - u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size; - unsigned int max_dma_count, len, period_count, i; dma_addr_t mem = buf_addr; int ret;