diff mbox series

[v1,3/4] dmaengine: hsu: Use GENMASK() consistently

Message ID 20220713172235.22611-3-andriy.shevchenko@linux.intel.com (mailing list archive)
State Accepted
Headers show
Series [v1,1/4] dmaengine: hsu: Finish conversion to managed resources | expand

Commit Message

Andy Shevchenko July 13, 2022, 5:22 p.m. UTC 
For the masks replace chain of BIT() macros by GENMASK().
While at it, explicitly include bits.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/hsu/hsu.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/dma/hsu/hsu.h b/drivers/dma/hsu/hsu.h
index 9e5956345748..1c1195709c2f 100644
--- a/drivers/dma/hsu/hsu.h
+++ b/drivers/dma/hsu/hsu.h
@@ -10,6 +10,7 @@ 
 #ifndef __DMA_HSU_H__
 #define __DMA_HSU_H__
 
+#include <linux/bits.h>
 #include <linux/spinlock.h>
 #include <linux/dma/hsu.h>
 
@@ -36,11 +37,11 @@ 
 
 /* Bits in HSU_CH_SR */
 #define HSU_CH_SR_DESCTO(x)	BIT(8 + (x))
-#define HSU_CH_SR_DESCTO_ANY	(BIT(11) | BIT(10) | BIT(9) | BIT(8))
+#define HSU_CH_SR_DESCTO_ANY	GENMASK(11, 8)
 #define HSU_CH_SR_CHE		BIT(15)
 #define HSU_CH_SR_DESCE(x)	BIT(16 + (x))
-#define HSU_CH_SR_DESCE_ANY	(BIT(19) | BIT(18) | BIT(17) | BIT(16))
-#define HSU_CH_SR_CDESC_ANY	(BIT(31) | BIT(30))
+#define HSU_CH_SR_DESCE_ANY	GENMASK(19, 16)
+#define HSU_CH_SR_CDESC_ANY	GENMASK(31, 30)
 
 /* Bits in HSU_CH_CR */
 #define HSU_CH_CR_CHA		BIT(0)