From patchwork Fri Jul 29 10:44:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12932311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B649C2BB9D for ; Fri, 29 Jul 2022 10:45:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235860AbiG2KpC (ORCPT ); Fri, 29 Jul 2022 06:45:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235820AbiG2KpB (ORCPT ); Fri, 29 Jul 2022 06:45:01 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2507E83223; Fri, 29 Jul 2022 03:44:57 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 74E196601B66; Fri, 29 Jul 2022 11:44:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091495; bh=TA74QxJMdtjbhlYPI6ogd09Z8LzPo3IXxmpuJNWStt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NAe69YGjki0F5pOABZw7N7isdxhWy81tV+oAU2rC2q+u/l4xSJGwvnjCmz1vPHpIa rA9bMPoiDIqNarvYBSJaH89J5/7EmB1GGp5PqlNLq50/TqwjV0xpb8BgfKuY6lnYX7 QdLPz6/pIeqlzMWxyTWaDtxuVu0MzsmP4nz/9vRi2myY3ZeZDiVbTuKvs3f5fMyK6H KyU89Xze+3VjsSa8BIW9kg7xQuXUyKFThy59ej1f6+AlP1SROSzIr0zE2958XJ735E 3JaxbkDq67zPK7JOVTSV0OfLEoE1N2VoBDoiRQDT2xAQc7moQV5TLNSlXL7kxh25aF eUcTq7GCvjw+w== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 3/8] arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets Date: Fri, 29 Jul 2022 12:44:35 +0200 Message-Id: <20220729104441.39177-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add nodes for topckgen, infracfg and pericfg, providing various clocks and resets and needed to support basic IPs of this SoC. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 46f0e54be766..9166d481a366 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -192,6 +192,26 @@ soc { compatible = "simple-bus"; ranges; + topckgen: syscon@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;