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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 17:18:35.6260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81cb2831-7d75-451b-64bb-08dac33f99d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7328 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6602fe421ee8..db479064ff72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA186_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -112,6 +113,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 28740c014f1d..fb073c459234 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -142,7 +142,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -176,6 +177,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5d7df32fd159..e1165b75f708 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -28,7 +28,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -61,6 +62,7 @@ ; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask = <0xfffffffe>; dma-coherent; };