From patchwork Fri Feb 17 09:39:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13144451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D234BC05027 for ; Fri, 17 Feb 2023 09:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230090AbjBQJkK (ORCPT ); Fri, 17 Feb 2023 04:40:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229605AbjBQJkK (ORCPT ); Fri, 17 Feb 2023 04:40:10 -0500 Received: from post.baikalelectronics.com (post.baikalelectronics.com [213.79.110.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5F7F562FDD; Fri, 17 Feb 2023 01:40:01 -0800 (PST) Received: from post.baikalelectronics.com (localhost.localdomain [127.0.0.1]) by post.baikalelectronics.com (Proxmox) with ESMTP id 80D55E0EAC; Fri, 17 Feb 2023 12:40:00 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= baikalelectronics.ru; h=cc:cc:content-transfer-encoding :content-type:content-type:date:from:from:in-reply-to:message-id :mime-version:references:reply-to:subject:subject:to:to; s=post; bh=Tv9FLsHiNOnxzHzQ4+Y5Gt8oNFskGfjGVuw49JYQI/M=; b=ry3EXBiKkYUA prt2XdNsZHFU/Tp461Whj35weJ3xp7uHhPpFj6uiaMMLWOBaejPJf3TFUBw/jyxF vB4M0OaLkpvFcZcULMd/waJ6x4fM8s0HRVAtaM8e2Ip6LniY/QIuZiagrWX7SAZM VnOz/4/F/qgIxrPtZNxfmOx5ztHqTbI= Received: from mail.baikal.int (mail.baikal.int [192.168.51.25]) by post.baikalelectronics.com (Proxmox) with ESMTP id 69CAEE0E6A; Fri, 17 Feb 2023 12:40:00 +0300 (MSK) Received: from localhost (10.8.30.14) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 17 Feb 2023 12:40:00 +0300 From: Serge Semin To: Bjorn Helgaas , Lorenzo Pieralisi , Cai Huoqing , Jingoo Han , Gustavo Pimentel , Vinod Koul , Manivannan Sadhasivam , Yoshihiro Shimoda , Rob Herring , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Vidya Sagar , Manivannan Sadhasivam CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , Subject: [PATCH 01/11] PCI: dwc: Fix port link CSR improper init if CDM check enabled Date: Fri, 17 Feb 2023 12:39:46 +0300 Message-ID: <20230217093956.27126-2-Sergey.Semin@baikalelectronics.ru> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230217093956.27126-1-Sergey.Semin@baikalelectronics.ru> References: <20230217093956.27126-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-Originating-IP: [10.8.30.14] X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org If CDM_CHECK capability is set then the local variable 'val' will be overwritten in the dw_pcie_setup() method in the PL_CHK register initialization procedure. Thus further variable usage in the framework of the PCIE_PORT_LINK_CONTROL register initialization must imply the variable re-initialization. Alas it hasn't been taken into account in the commit ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists"). Due to that the PCIE_PORT_LINK_CONTROL register will be written with improper value in case if the CDM-check is enabled. Let's fix this by re-initializing the 'val' variable with the PCIE_PORT_LINK_CONTROL CSR content before link-mode initialization. Fixes: ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists") Signed-off-by: Serge Semin --- drivers/pci/controller/dwc/pcie-designware.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d5d619ab2e9..3bb9ca14fb9c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -824,6 +824,7 @@ void dw_pcie_setup(struct dw_pcie *pci) } /* Set the number of lanes */ + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_FAST_LINK_MODE; val &= ~PORT_LINK_MODE_MASK; switch (pci->num_lanes) {