From patchwork Mon Mar 6 14:04:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walker Chen X-Patchwork-Id: 13161122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DE23C678D4 for ; Mon, 6 Mar 2023 14:05:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230015AbjCFOFJ (ORCPT ); Mon, 6 Mar 2023 09:05:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbjCFOE5 (ORCPT ); Mon, 6 Mar 2023 09:04:57 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 120002595E; Mon, 6 Mar 2023 06:04:46 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id BF6A324DBC0; Mon, 6 Mar 2023 22:04:43 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 22:04:43 +0800 Received: from localhost.localdomain (183.27.97.46) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 22:04:43 +0800 From: Walker Chen To: Eugeniy Paltsev , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , "Emil Renner Berthing" , Walker Chen CC: , , , Subject: [PATCH v4 2/3] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA Date: Mon, 6 Mar 2023 22:04:29 +0800 Message-ID: <20230306140430.28951-3-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230306140430.28951-1-walker.chen@starfivetech.com> References: <20230306140430.28951-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.46] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma reset operation in device probe and use different configuration on CH_CFG registers according to match data. Update all uses of of_device_is_compatible with of_device_get_match_data. Reviewed-by: Emil Renner Berthing Signed-off-by: Walker Chen --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 67 ++++++++++++++++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 + 2 files changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index bf85aa0979ec..d1148f6fbcf9 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -21,10 +21,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -46,6 +48,12 @@ DMA_SLAVE_BUSWIDTH_32_BYTES | \ DMA_SLAVE_BUSWIDTH_64_BYTES) +struct axi_dma_chip_config { + int (*apb_setup)(struct platform_device *pdev, struct axi_dma_chip *chip); + int (*reset_init)(struct platform_device *pdev); + bool use_cfg2; +}; + static inline void axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) { @@ -86,7 +94,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan, cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); - if (chan->chip->dw->hdata->reg_map_8_channels) { + if (chan->chip->dw->hdata->reg_map_8_channels && + !chan->chip->dw->hdata->use_cfg2) { cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | @@ -1142,7 +1151,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan) axi_chan_disable(chan); ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, - !(val & chan_active), 1000, 10000); + !(val & chan_active), 1000, DMAC_TIMEOUT_US); if (ret == -ETIMEDOUT) dev_warn(dchan2dev(dchan), "%s failed to stop\n", axi_chan_name(chan)); @@ -1367,13 +1376,33 @@ static int parse_device_properties(struct axi_dma_chip *chip) return 0; } +static int intel_apb_setup(struct platform_device *pdev, struct axi_dma_chip *chip) +{ + chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->apb_regs)) + return PTR_ERR(chip->apb_regs); + else + return 0; +} + +static int jh7110_reset_init(struct platform_device *pdev) +{ + struct reset_control *resets; + + resets = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(resets)) + return PTR_ERR(resets); + + return reset_control_deassert(resets); +} + static int dw_probe(struct platform_device *pdev) { - struct device_node *node = pdev->dev.of_node; struct axi_dma_chip *chip; struct resource *mem; struct dw_axi_dma *dw; struct dw_axi_dma_hcfg *hdata; + const struct axi_dma_chip_config *ccfg; u32 i; int ret; @@ -1402,10 +1431,21 @@ static int dw_probe(struct platform_device *pdev) if (IS_ERR(chip->regs)) return PTR_ERR(chip->regs); - if (of_device_is_compatible(node, "intel,kmb-axi-dma")) { - chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->apb_regs)) - return PTR_ERR(chip->apb_regs); + ccfg = of_device_get_match_data(&pdev->dev); + if (ccfg) { + if (ccfg->apb_setup) { + ret = ccfg->apb_setup(pdev, chip); + if (ret) + return ret; + } + + if (ccfg->reset_init) { + ret = ccfg->reset_init(pdev); + if (ret) + return ret; + } + + chip->dw->hdata->use_cfg2 = ccfg->use_cfg2; } chip->core_clk = devm_clk_get(chip->dev, "core-clk"); @@ -1557,9 +1597,20 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = { SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) }; +static const struct axi_dma_chip_config intel_chip_config = { + .apb_setup = intel_apb_setup, + .use_cfg2 = false, +}; + +static const struct axi_dma_chip_config jh7110_chip_config = { + .reset_init = jh7110_reset_init, + .use_cfg2 = true, +}; + static const struct of_device_id dw_dma_of_id_table[] = { { .compatible = "snps,axi-dma-1.01a" }, - { .compatible = "intel,kmb-axi-dma" }, + { .compatible = "intel,kmb-axi-dma", .data = &intel_chip_config }, + { .compatible = "starfive,jh7110-axi-dma", .data = &jh7110_chip_config }, {} }; MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index e9d5eb0fd594..b906d5884efe 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -21,6 +21,7 @@ #define DMAC_MAX_CHANNELS 16 #define DMAC_MAX_MASTERS 2 #define DMAC_MAX_BLK_SIZE 0x200000 +#define DMAC_TIMEOUT_US 200000 struct dw_axi_dma_hcfg { u32 nr_channels; @@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg { /* Register map for DMAX_NUM_CHANNELS <= 8 */ bool reg_map_8_channels; bool restrict_axi_burst_len; + bool use_cfg2; }; struct axi_dma_chan {