| Message ID | 20231031025511.1516342-3-guanjun@linux.alibaba.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Some fixes for idxd driver | expand |
On 10/30/2023 9:55 PM, 'Guanjun' wrote: > From: Guanjun <guanjun@linux.alibaba.com> > > Fix incorrect descriptions for the GRPCFG register which has three > sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG). > No functional changes > > Signed-off-by: Guanjun <guanjun@linux.alibaba.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> > --- Acked-by: Lijun Pan <lijun.pan@intel.com> > drivers/dma/idxd/registers.h | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h > index 7b54a3939ea1..315c004f58e4 100644 > --- a/drivers/dma/idxd/registers.h > +++ b/drivers/dma/idxd/registers.h > @@ -440,12 +440,14 @@ union wqcfg { > /* > * This macro calculates the offset into the GRPCFG register > * idxd - struct idxd * > - * n - wq id > - * ofs - the index of the 32b dword for the config register > + * n - group id > + * ofs - the index of the 64b qword for the config register > * > - * The WQCFG register block is divided into groups per each wq. The n index > - * allows us to move to the register group that's for that particular wq. > - * Each register is 32bits. The ofs gives us the number of register to access. > + * The GRPCFG register block is divided into three sub-registers, which > + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move > + * to the register block that contains the three sub-registers. > + * Each register block is 64bits. And the ofs gives us the offset > + * within the GRPWQCFG register to access. > */ > #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ > (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..315c004f58e4 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,14 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to access. + * The GRPCFG register block is divided into three sub-registers, which + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move + * to the register block that contains the three sub-registers. + * Each register block is 64bits. And the ofs gives us the offset + * within the GRPWQCFG register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))