From patchwork Thu Nov 30 11:13:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13474239 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MzRXhGDF" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDEEA1B3 for ; Thu, 30 Nov 2023 03:13:18 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id ECE76E0002; Thu, 30 Nov 2023 11:13:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701342797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gr9l/ohpsYqUsnTKIffKhuISxG6OBCvmKdftALlQWbg=; b=MzRXhGDFx1aKcGw2pj79yJFvsqy0O27rnfTvneb2m0Kgk4OcftiykHGFrrnvcGIx+B6HMC jPMNu1aFu4p5SeD/jz8PTqcBiOwpLsLraEHR6PpUyUIBKCeRuFSZLx3ZzHqByoMuAXgMyc D6Ju4QWDhBxrsThsK1vaAjcnk4BKMZc1hco92ZPpASlYjIVa7xxU7W5TLn4tuwI8iZj26u A8SZVLLx+pRvQMFyHrJxFJ2B3WjYUdBMtFZUY0/NBZtsevD7khGEJEBCJ3qg6RdtYFDF2c 8LBd/PuO9j1MeeDTlTHJhPY/BeJD2a6v4j4srKIenEQzr4FfGnFr7qnUyj8u3g== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul Cc: Thomas Petazzoni , Michal Simek , dmaengine@vger.kernel.org, Miquel Raynal Subject: [PATCH v2 1/4] dmaengine: xilinx: xdma: Fix the count of elapsed periods in cyclic mode Date: Thu, 30 Nov 2023 12:13:12 +0100 Message-Id: <20231130111315.729430-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com> References: <20231130111315.729430-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com Xilinx DMA engine is capable of keeping track of the number of elapsed periods and this is an increasing 32-bit counter which is only reset when turning off the engine. No need to add this value to our local counter. Fixes: cd8c732ce1a5 ("dmaengine: xilinx: xdma: Support cyclic transfers") Signed-off-by: Miquel Raynal --- Hello, so far all my testing was performed by looping the playback output to the recording input and comparing the files using FFTs. Unfortunately, when the DMA engine suffers from the same issue on both sides, some issues may appear un-noticed, which is likely what happened here as the tooling did not report any issue while analyzing the output until I actually listened to real audio now that I have in my hands the relevant hardware/connectors to do so. --- drivers/dma/xilinx/xdma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 84a88029226f..2c9c72d4b5a2 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -754,9 +754,9 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) if (ret) goto out; - desc->completed_desc_num += complete_desc_num; - if (desc->cyclic) { + desc->completed_desc_num = complete_desc_num; + ret = regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, &st); if (ret) @@ -768,6 +768,8 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) goto out; } + desc->completed_desc_num += complete_desc_num; + /* * if all data blocks are transferred, remove and complete the request */