diff mbox series

[1/1] dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read

Message ID 20240201215007.439503-1-Frank.Li@nxp.com (mailing list archive)
State Accepted
Commit 9d739bccf261dd93ec1babf82f5c5d71dd4caa3e
Headers show
Series [1/1] dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read | expand

Commit Message

Frank Li Feb. 1, 2024, 9:50 p.m. UTC 
From: Peng Ma <peng.ma@nxp.com>

There is chip (ls1028a) errata:

The SoC may hang on 16 byte unaligned read transactions by QDMA.

Unaligned read transactions initiated by QDMA may stall in the NOC
(Network On-Chip), causing a deadlock condition. Stalled transactions will
trigger completion timeouts in PCIe controller.

Workaround:
Enable prefetch by setting the source descriptor prefetchable bit
( SD[PF] = 1 ).

Implement this workaround.

Cc: stable@vger.kernel.org
Fixes: b092529e0aa0 ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-qdma.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Vinod Koul Feb. 7, 2024, 8:49 a.m. UTC | #1 
On Thu, 01 Feb 2024 16:50:07 -0500, Frank Li wrote:
> There is chip (ls1028a) errata:
> 
> The SoC may hang on 16 byte unaligned read transactions by QDMA.
> 
> Unaligned read transactions initiated by QDMA may stall in the NOC
> (Network On-Chip), causing a deadlock condition. Stalled transactions will
> trigger completion timeouts in PCIe controller.
> 
> [...]

Applied, thanks!

[1/1] dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read
      commit: 9d739bccf261dd93ec1babf82f5c5d71dd4caa3e

Best regards,
diff mbox series

Patch

diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index 47cb284680494..11d10dcd8b45d 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -109,6 +109,7 @@ 
 #define FSL_QDMA_CMD_WTHROTL_OFFSET	20
 #define FSL_QDMA_CMD_DSEN_OFFSET	19
 #define FSL_QDMA_CMD_LWC_OFFSET		16
+#define FSL_QDMA_CMD_PF			BIT(17)
 
 /* Field definition for Descriptor status */
 #define QDMA_CCDF_STATUS_RTE		BIT(5)
@@ -384,7 +385,8 @@  static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
 	qdma_csgf_set_f(csgf_dest, len);
 	/* Descriptor Buffer */
 	cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
-			  FSL_QDMA_CMD_RWTTYPE_OFFSET);
+			  FSL_QDMA_CMD_RWTTYPE_OFFSET) |
+			  FSL_QDMA_CMD_PF;
 	sdf->data = QDMA_SDDF_CMD(cmd);
 
 	cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<