diff mbox series

[v3,5/7] dmaengine: ae4dma: Register AE4DMA using pt_dmaengine_register

Message ID 20240624075610.1659502-6-Basavaraj.Natikar@amd.com (mailing list archive)
State New
Headers show
Series Add support of AMD AE4DMA DMA Engine | expand

Commit Message

Basavaraj Natikar June 24, 2024, 7:56 a.m. UTC 
Use the pt_dmaengine_register function to register a AE4DMA DMA engine.

Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
---
 drivers/dma/amd/ae4dma/ae4dma-dev.c     | 65 +++++++++++++++++++++++++
 drivers/dma/amd/ae4dma/ae4dma-pci.c     |  1 +
 drivers/dma/amd/ae4dma/ae4dma.h         |  2 +
 drivers/dma/amd/ptdma/ptdma-dmaengine.c |  1 +
 4 files changed, 69 insertions(+)

Comments

Philipp Stanner June 24, 2024, 8:38 a.m. UTC | #1 
On Mon, 2024-06-24 at 13:26 +0530, Basavaraj Natikar wrote:
> Use the pt_dmaengine_register function to register a AE4DMA DMA
> engine.
> 
> Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com>
> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
> ---
>  drivers/dma/amd/ae4dma/ae4dma-dev.c     | 65
> +++++++++++++++++++++++++
>  drivers/dma/amd/ae4dma/ae4dma-pci.c     |  1 +
>  drivers/dma/amd/ae4dma/ae4dma.h         |  2 +
>  drivers/dma/amd/ptdma/ptdma-dmaengine.c |  1 +
>  4 files changed, 69 insertions(+)
> 
> diff --git a/drivers/dma/amd/ae4dma/ae4dma-dev.c
> b/drivers/dma/amd/ae4dma/ae4dma-dev.c
> index cb05fcb47987..9ab74fc227cb 100644
> --- a/drivers/dma/amd/ae4dma/ae4dma-dev.c
> +++ b/drivers/dma/amd/ae4dma/ae4dma-dev.c
> @@ -58,6 +58,15 @@ static void ae4_check_status_error(struct
> ae4_cmd_queue *ae4cmd_q, int idx)
>         }
>  }
>  
> +void pt_check_status_trans(struct pt_device *pt, struct pt_cmd_queue
> *cmd_q)
> +{
> +       struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct
> ae4_cmd_queue, cmd_q);
> +       int i;
> +
> +       for (i = 0; i < CMD_Q_LEN; i++)
> +               ae4_check_status_error(ae4cmd_q, i);
> +}
> +
>  static void ae4_pending_work(struct work_struct *work)
>  {
>         struct ae4_cmd_queue *ae4cmd_q = container_of(work, struct
> ae4_cmd_queue, p_work.work);
> @@ -117,6 +126,58 @@ static irqreturn_t ae4_core_irq_handler(int irq,
> void *data)
>         return IRQ_HANDLED;
>  }
>  
> +static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct
> ae4_cmd_queue *ae4cmd_q)
> +{
> +       bool soc = FIELD_GET(DWORD0_SOC, desc->dwouv.dw0);
> +       struct pt_cmd_queue *cmd_q = &ae4cmd_q->cmd_q;
> +
> +       if (soc) {
> +               desc->dwouv.dw0 |= FIELD_PREP(DWORD0_IOC, desc-
> >dwouv.dw0);
> +               desc->dwouv.dw0 &= ~DWORD0_SOC;
> +       }
> +
> +       mutex_lock(&ae4cmd_q->cmd_lock);
> +
> +       memcpy(&cmd_q->qbase[ae4cmd_q->tail_wi], desc, sizeof(struct
> ae4dma_desc));
> +
> +       ae4cmd_q->q_cmd_count++;
> +
> +       ae4cmd_q->tail_wi = (ae4cmd_q->tail_wi + 1) % CMD_Q_LEN;
> +
> +       writel(ae4cmd_q->tail_wi, cmd_q->reg_control + 0x10);

magic number 0x10?

> +
> +       mutex_unlock(&ae4cmd_q->cmd_lock);
> +
> +       wake_up(&ae4cmd_q->q_w);

nit: I'd remove the blank lines and create a block consisting of the
mutexes.

Thanks,
P.


> +
> +       return 0;
> +}
> +
> +int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q,
> +                            struct pt_passthru_engine *pt_engine)
> +{
> +       struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct
> ae4_cmd_queue, cmd_q);
> +       struct ae4dma_desc desc;
> +
> +       cmd_q->cmd_error = 0;
> +       cmd_q->total_pt_ops++;
> +       memset(&desc, 0, sizeof(desc));
> +       desc.dwouv.dws.byte0 = CMD_AE4_DESC_DW0_VAL;
> +
> +       desc.dw1.status = 0;
> +       desc.dw1.err_code = 0;
> +       desc.dw1.desc_id = 0;
> +
> +       desc.length = pt_engine->src_len;
> +
> +       desc.src_lo = upper_32_bits(pt_engine->src_dma);
> +       desc.src_hi = lower_32_bits(pt_engine->src_dma);
> +       desc.dst_lo = upper_32_bits(pt_engine->dst_dma);
> +       desc.dst_hi = lower_32_bits(pt_engine->dst_dma);
> +
> +       return ae4_core_execute_cmd(&desc, ae4cmd_q);
> +}
> +
>  void ae4_destroy_work(struct ae4_device *ae4)
>  {
>         struct ae4_cmd_queue *ae4cmd_q;
> @@ -196,5 +257,9 @@ int ae4_core_init(struct ae4_device *ae4)
>                 init_completion(&ae4cmd_q->cmp);
>         }
>  
> +       ret = pt_dmaengine_register(pt);
> +       if (ret)
> +               ae4_destroy_work(ae4);
> +
>         return ret;
>  }
> diff --git a/drivers/dma/amd/ae4dma/ae4dma-pci.c
> b/drivers/dma/amd/ae4dma/ae4dma-pci.c
> index 43d36e9d1efb..aad0dc4294a3 100644
> --- a/drivers/dma/amd/ae4dma/ae4dma-pci.c
> +++ b/drivers/dma/amd/ae4dma/ae4dma-pci.c
> @@ -98,6 +98,7 @@ static int ae4_pci_probe(struct pci_dev *pdev,
> const struct pci_device_id *id)
>  
>         pt = &ae4->pt;
>         pt->dev = dev;
> +       pt->ver = AE4_DMA_VERSION;
>  
>         pt->io_regs = pcim_iomap_table(pdev)[0];
>         if (!pt->io_regs) {
> diff --git a/drivers/dma/amd/ae4dma/ae4dma.h
> b/drivers/dma/amd/ae4dma/ae4dma.h
> index 850ad1e49b51..668fad780314 100644
> --- a/drivers/dma/amd/ae4dma/ae4dma.h
> +++ b/drivers/dma/amd/ae4dma/ae4dma.h
> @@ -16,6 +16,7 @@
>  
>  #define AE4_DESC_COMPLETED             0x3
>  #define AE4_DMA_VERSION                        4
> +#define CMD_AE4_DESC_DW0_VAL           2
>  
>  struct ae4_msix {
>         int msix_count;
> @@ -36,6 +37,7 @@ struct ae4_cmd_queue {
>         atomic64_t done_cnt;
>         u64 q_cmd_count;
>         u32 dridx;
> +       u32 tail_wi;
>         u32 id;
>  };
>  
> diff --git a/drivers/dma/amd/ptdma/ptdma-dmaengine.c
> b/drivers/dma/amd/ptdma/ptdma-dmaengine.c
> index 90ca02fd5f8f..1f020f90d886 100644
> --- a/drivers/dma/amd/ptdma/ptdma-dmaengine.c
> +++ b/drivers/dma/amd/ptdma/ptdma-dmaengine.c
> @@ -462,6 +462,7 @@ int pt_dmaengine_register(struct pt_device *pt)
>  
>         return ret;
>  }
> +EXPORT_SYMBOL_GPL(pt_dmaengine_register);
>  
>  void pt_dmaengine_unregister(struct pt_device *pt)
>  {
diff mbox series

Patch

diff --git a/drivers/dma/amd/ae4dma/ae4dma-dev.c b/drivers/dma/amd/ae4dma/ae4dma-dev.c
index cb05fcb47987..9ab74fc227cb 100644
--- a/drivers/dma/amd/ae4dma/ae4dma-dev.c
+++ b/drivers/dma/amd/ae4dma/ae4dma-dev.c
@@ -58,6 +58,15 @@  static void ae4_check_status_error(struct ae4_cmd_queue *ae4cmd_q, int idx)
 	}
 }
 
+void pt_check_status_trans(struct pt_device *pt, struct pt_cmd_queue *cmd_q)
+{
+	struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct ae4_cmd_queue, cmd_q);
+	int i;
+
+	for (i = 0; i < CMD_Q_LEN; i++)
+		ae4_check_status_error(ae4cmd_q, i);
+}
+
 static void ae4_pending_work(struct work_struct *work)
 {
 	struct ae4_cmd_queue *ae4cmd_q = container_of(work, struct ae4_cmd_queue, p_work.work);
@@ -117,6 +126,58 @@  static irqreturn_t ae4_core_irq_handler(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct ae4_cmd_queue *ae4cmd_q)
+{
+	bool soc = FIELD_GET(DWORD0_SOC, desc->dwouv.dw0);
+	struct pt_cmd_queue *cmd_q = &ae4cmd_q->cmd_q;
+
+	if (soc) {
+		desc->dwouv.dw0 |= FIELD_PREP(DWORD0_IOC, desc->dwouv.dw0);
+		desc->dwouv.dw0 &= ~DWORD0_SOC;
+	}
+
+	mutex_lock(&ae4cmd_q->cmd_lock);
+
+	memcpy(&cmd_q->qbase[ae4cmd_q->tail_wi], desc, sizeof(struct ae4dma_desc));
+
+	ae4cmd_q->q_cmd_count++;
+
+	ae4cmd_q->tail_wi = (ae4cmd_q->tail_wi + 1) % CMD_Q_LEN;
+
+	writel(ae4cmd_q->tail_wi, cmd_q->reg_control + 0x10);
+
+	mutex_unlock(&ae4cmd_q->cmd_lock);
+
+	wake_up(&ae4cmd_q->q_w);
+
+	return 0;
+}
+
+int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q,
+			     struct pt_passthru_engine *pt_engine)
+{
+	struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct ae4_cmd_queue, cmd_q);
+	struct ae4dma_desc desc;
+
+	cmd_q->cmd_error = 0;
+	cmd_q->total_pt_ops++;
+	memset(&desc, 0, sizeof(desc));
+	desc.dwouv.dws.byte0 = CMD_AE4_DESC_DW0_VAL;
+
+	desc.dw1.status = 0;
+	desc.dw1.err_code = 0;
+	desc.dw1.desc_id = 0;
+
+	desc.length = pt_engine->src_len;
+
+	desc.src_lo = upper_32_bits(pt_engine->src_dma);
+	desc.src_hi = lower_32_bits(pt_engine->src_dma);
+	desc.dst_lo = upper_32_bits(pt_engine->dst_dma);
+	desc.dst_hi = lower_32_bits(pt_engine->dst_dma);
+
+	return ae4_core_execute_cmd(&desc, ae4cmd_q);
+}
+
 void ae4_destroy_work(struct ae4_device *ae4)
 {
 	struct ae4_cmd_queue *ae4cmd_q;
@@ -196,5 +257,9 @@  int ae4_core_init(struct ae4_device *ae4)
 		init_completion(&ae4cmd_q->cmp);
 	}
 
+	ret = pt_dmaengine_register(pt);
+	if (ret)
+		ae4_destroy_work(ae4);
+
 	return ret;
 }
diff --git a/drivers/dma/amd/ae4dma/ae4dma-pci.c b/drivers/dma/amd/ae4dma/ae4dma-pci.c
index 43d36e9d1efb..aad0dc4294a3 100644
--- a/drivers/dma/amd/ae4dma/ae4dma-pci.c
+++ b/drivers/dma/amd/ae4dma/ae4dma-pci.c
@@ -98,6 +98,7 @@  static int ae4_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
 	pt = &ae4->pt;
 	pt->dev = dev;
+	pt->ver = AE4_DMA_VERSION;
 
 	pt->io_regs = pcim_iomap_table(pdev)[0];
 	if (!pt->io_regs) {
diff --git a/drivers/dma/amd/ae4dma/ae4dma.h b/drivers/dma/amd/ae4dma/ae4dma.h
index 850ad1e49b51..668fad780314 100644
--- a/drivers/dma/amd/ae4dma/ae4dma.h
+++ b/drivers/dma/amd/ae4dma/ae4dma.h
@@ -16,6 +16,7 @@ 
 
 #define AE4_DESC_COMPLETED		0x3
 #define AE4_DMA_VERSION			4
+#define CMD_AE4_DESC_DW0_VAL		2
 
 struct ae4_msix {
 	int msix_count;
@@ -36,6 +37,7 @@  struct ae4_cmd_queue {
 	atomic64_t done_cnt;
 	u64 q_cmd_count;
 	u32 dridx;
+	u32 tail_wi;
 	u32 id;
 };
 
diff --git a/drivers/dma/amd/ptdma/ptdma-dmaengine.c b/drivers/dma/amd/ptdma/ptdma-dmaengine.c
index 90ca02fd5f8f..1f020f90d886 100644
--- a/drivers/dma/amd/ptdma/ptdma-dmaengine.c
+++ b/drivers/dma/amd/ptdma/ptdma-dmaengine.c
@@ -462,6 +462,7 @@  int pt_dmaengine_register(struct pt_device *pt)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(pt_dmaengine_register);
 
 void pt_dmaengine_unregister(struct pt_device *pt)
 {