| Message ID | 20240808100024.317497-3-abin.joseph@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 13113f750a4ae0b1770fa25dc94852977ebfb942 |
| Headers | show |
| Series | Add support for ADMA | expand |
> -----Original Message----- > From: Abin Joseph <abin.joseph@amd.com> > Sent: Thursday, August 8, 2024 3:30 PM > To: vkoul@kernel.org; Simek, Michal <michal.simek@amd.com>; > robh@kernel.org; conor+dt@kernel.org; krzk+dt@kernel.org; u.kleine- > koenig@pengutronix.de; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com>; Katakam, Harini > <harini.katakam@amd.com> > Cc: git (AMD-Xilinx) <git@amd.com>; Joseph, Abin > <Abin.Joseph@amd.com>; dmaengine@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: [PATCH v2 2/2] dmaengine: zynqmp_dma: Add support for AMD > Versal Gen 2 DMA IP > > ZynqMP DMA IP and AMD Versal Gen 2 DMA IP are similar but have different > interrupt register offset. Create a dedicated compatible string to > support Versal Gen 2 DMA IP with Irq register offset for interrupt > Enable/Disable/Status/Mask functionality. > > Signed-off-by: Abin Joseph <abin.joseph@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Thanks! > --- > > Changes in v2: > - Update the logic to use of_device_get_match_data > instead of of_device_is_compatible. > - Use lower case hexa decimal value for macros. > > --- > drivers/dma/xilinx/zynqmp_dma.c | 27 +++++++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/xilinx/zynqmp_dma.c > b/drivers/dma/xilinx/zynqmp_dma.c > index f31631bef961..9ae46f1198fe 100644 > --- a/drivers/dma/xilinx/zynqmp_dma.c > +++ b/drivers/dma/xilinx/zynqmp_dma.c > @@ -22,10 +22,10 @@ > #include "../dmaengine.h" > > /* Register Offsets */ > -#define ZYNQMP_DMA_ISR 0x100 > -#define ZYNQMP_DMA_IMR 0x104 > -#define ZYNQMP_DMA_IER 0x108 > -#define ZYNQMP_DMA_IDS 0x10C > +#define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100) > +#define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104) > +#define ZYNQMP_DMA_IER (chan->irq_offset + 0x108) > +#define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c) > #define ZYNQMP_DMA_CTRL0 0x110 > #define ZYNQMP_DMA_CTRL1 0x114 > #define ZYNQMP_DMA_DATA_ATTR 0x120 > @@ -145,6 +145,9 @@ > #define tx_to_desc(tx) container_of(tx, struct > zynqmp_dma_desc_sw, \ > async_tx) > > +/* IRQ Register offset for Versal Gen 2 */ > +#define IRQ_REG_OFFSET 0x308 > + > /** > * struct zynqmp_dma_desc_ll - Hw linked list descriptor > * @addr: Buffer address > @@ -211,6 +214,7 @@ struct zynqmp_dma_desc_sw { > * @bus_width: Bus width > * @src_burst_len: Source burst length > * @dst_burst_len: Dest burst length > + * @irq_offset: Irq register offset > */ > struct zynqmp_dma_chan { > struct zynqmp_dma_device *zdev; > @@ -235,6 +239,7 @@ struct zynqmp_dma_chan { > u32 bus_width; > u32 src_burst_len; > u32 dst_burst_len; > + u32 irq_offset; > }; > > /** > @@ -253,6 +258,14 @@ struct zynqmp_dma_device { > struct clk *clk_apb; > }; > > +struct zynqmp_dma_config { > + u32 offset; > +}; > + > +static const struct zynqmp_dma_config versal2_dma_config = { > + .offset = IRQ_REG_OFFSET, > +}; > + > static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 > reg, > u64 value) > { > @@ -892,6 +905,7 @@ static int zynqmp_dma_chan_probe(struct > zynqmp_dma_device *zdev, > { > struct zynqmp_dma_chan *chan; > struct device_node *node = pdev->dev.of_node; > + const struct zynqmp_dma_config *match_data; > int err; > > chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL); > @@ -919,6 +933,10 @@ static int zynqmp_dma_chan_probe(struct > zynqmp_dma_device *zdev, > return -EINVAL; > } > > + match_data = of_device_get_match_data(&pdev->dev); > + if (match_data) > + chan->irq_offset = match_data->offset; > + > chan->is_dmacoherent = of_property_read_bool(node, "dma- > coherent"); > zdev->chan = chan; > tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); > @@ -1161,6 +1179,7 @@ static void zynqmp_dma_remove(struct > platform_device *pdev) > } > > static const struct of_device_id zynqmp_dma_of_match[] = { > + { .compatible = "amd,versal2-dma-1.0", .data = &versal2_dma_config > }, > { .compatible = "xlnx,zynqmp-dma-1.0", }, > {} > }; > -- > 2.34.1
diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index f31631bef961..9ae46f1198fe 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -22,10 +22,10 @@ #include "../dmaengine.h" /* Register Offsets */ -#define ZYNQMP_DMA_ISR 0x100 -#define ZYNQMP_DMA_IMR 0x104 -#define ZYNQMP_DMA_IER 0x108 -#define ZYNQMP_DMA_IDS 0x10C +#define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100) +#define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104) +#define ZYNQMP_DMA_IER (chan->irq_offset + 0x108) +#define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c) #define ZYNQMP_DMA_CTRL0 0x110 #define ZYNQMP_DMA_CTRL1 0x114 #define ZYNQMP_DMA_DATA_ATTR 0x120 @@ -145,6 +145,9 @@ #define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \ async_tx) +/* IRQ Register offset for Versal Gen 2 */ +#define IRQ_REG_OFFSET 0x308 + /** * struct zynqmp_dma_desc_ll - Hw linked list descriptor * @addr: Buffer address @@ -211,6 +214,7 @@ struct zynqmp_dma_desc_sw { * @bus_width: Bus width * @src_burst_len: Source burst length * @dst_burst_len: Dest burst length + * @irq_offset: Irq register offset */ struct zynqmp_dma_chan { struct zynqmp_dma_device *zdev; @@ -235,6 +239,7 @@ struct zynqmp_dma_chan { u32 bus_width; u32 src_burst_len; u32 dst_burst_len; + u32 irq_offset; }; /** @@ -253,6 +258,14 @@ struct zynqmp_dma_device { struct clk *clk_apb; }; +struct zynqmp_dma_config { + u32 offset; +}; + +static const struct zynqmp_dma_config versal2_dma_config = { + .offset = IRQ_REG_OFFSET, +}; + static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg, u64 value) { @@ -892,6 +905,7 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, { struct zynqmp_dma_chan *chan; struct device_node *node = pdev->dev.of_node; + const struct zynqmp_dma_config *match_data; int err; chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL); @@ -919,6 +933,10 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, return -EINVAL; } + match_data = of_device_get_match_data(&pdev->dev); + if (match_data) + chan->irq_offset = match_data->offset; + chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); zdev->chan = chan; tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); @@ -1161,6 +1179,7 @@ static void zynqmp_dma_remove(struct platform_device *pdev) } static const struct of_device_id zynqmp_dma_of_match[] = { + { .compatible = "amd,versal2-dma-1.0", .data = &versal2_dma_config }, { .compatible = "xlnx,zynqmp-dma-1.0", }, {} };
ZynqMP DMA IP and AMD Versal Gen 2 DMA IP are similar but have different interrupt register offset. Create a dedicated compatible string to support Versal Gen 2 DMA IP with Irq register offset for interrupt Enable/Disable/Status/Mask functionality. Signed-off-by: Abin Joseph <abin.joseph@amd.com> --- Changes in v2: - Update the logic to use of_device_get_match_data instead of of_device_is_compatible. - Use lower case hexa decimal value for macros. --- drivers/dma/xilinx/zynqmp_dma.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-)