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Wed, 18 Sep 2024 13:10:25 -0500 From: Lizhi Hou To: , CC: Lizhi Hou , , , Subject: [PATCH V1 1/1] dmaengine: amd: qdma: Remove using the private get and set dma_ops APIs Date: Wed, 18 Sep 2024 11:10:22 -0700 Message-ID: <20240918181022.2155715-1-lizhi.hou@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: lizhi.hou@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|LV8PR12MB9208:EE_ X-MS-Office365-Filtering-Correlation-Id: 72797a87-ca7a-4fa8-7a13-08dcd80d2c75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: 47w2JqktNUQqu/f/7slVylvwL84aN5/R23/d8klOdkT/8sCs10ntktGxeAlY2wjIO82u8clgY1B9hV8Ld2nYssxowy2HQ5cEcQV1ftZJRfPZ8tqzhERKpxNasQeWOumdUtJ4AJpZT04NI+S9Gi3j3ASPcg0m6DA4zOYtDT7AwxJ1nljop5C5MVEgKBqEG1tcgmNn/vHnwfT0KFiWNNrXQmvx4OBTCAQofZicHuwE/8uDwAy/6FGxmjVA5/jExSmkOlbpqp5wMRrk24HY7E7vXOF/9KQWYYl/UWtPj49nDQwQDmfrBdrP5WOGnMemgt3MTcJx3Mb4rUvOD/CQg/hSwyJiB8trngPpgq+VohcrdhIhQS/j2HRBS6DmuzVfIgrbGEyEVYMpWJcn7+pO0DUu7+ipKawkHpzfKUNYavD20KZOsUDDmxD+phUoYy9hJDVc4nWfuF8SjohWiP5vRlgbgSty23in5jSaD+ChjjF6IA4z/twAK2lK4ToM9rFZjyUtsHp9P7DFVWojjcAur0ymFDhQ8EwFbrd+JLdx0DhBjnyGr2qbgfsIBZnfcoZvh916Y2OGaFjX8w5NVb9OVeDjd5F/Bo9DI+eOzT+J/CDNiCoh+e1EO4sruYYbz6X4Ts2uyN0tdpFDHY4TUhD2Ueqgro9YR5YgFRPDWYCmpUEetguNBZH5mc/2i/w+hSOmqGRSuY88gbaKJgHi3Th9FeFmPlPolKBt0sFYsLVw9xc6uwjsNOECw0G1yewyF0LqZKx1lzVmjXY2wtmGnzVwjKqoaYWGHoqge1Unpl9jJJWclMaVbCuEjbYMrKtRepqF1/87o4FMB9YrUHu/PFJ7FCDspiVs/JGXsuQ0nXbYMv1GCXQlhXaG9hTnhKsyH+nyHR45piMd4A2YUwflMVlI2d5Ehz28IflJhXgB04lqBxS5aUyde95lEnH3J0phf5kcHDRNhpTRz/RkXOBD9DVAIQI530sS1oSNz6nLxUhx9+Yx3OmjWm6WJfpHZ7OBfViWCB6ZTUKXW+msyaPy9WUZeSfPnjedhjDXSqB5j6TuH3rwaHMcQkiyZm1Y8eoyOAtI5hy7FKxleWBlPOwPadkq8Wwe76YQVjr8rACiV1n5wJ9ToaiKQ3k0/j2T+49JJMTn6DZwsYzTwPn4i0o7xOvCN5KM07LsOn/jKhV93fPPlzjmnz617/jSSx7Fx8yFV8g9kqO/S/uy7yZ17KqqW0FPZMNm8368HrmoVPQgu8KPnSQQ5tVCKpEpt2CyJt0YLTWmQtO8Gd0pRrlCogEItdg8cFNxQX2aGwRuaVl3GfNpWGA1R1bz9nAvdWuh8X51/hgNh6xl2Q1Jo0TMInLFx8Ux6LXPRwZYWa9vsWdCO2tulslOtU8rup3sEJxGKEglTzHsF3NieUU6hZDNSTBhBjQGQP6V0+z/Gkdnz8+3yYdLqkDjEHUWy4JBae9/k6TP+nHO7Pt8 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 18:10:27.1057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72797a87-ca7a-4fa8-7a13-08dcd80d2c75 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9208 The get_dma_ops and set_dma_ops APIs were never for driver to use. Remove these calls from QDMA driver. Instead, pass the DMA device pointer from the qdma_platdata structure. Fixes: 73d5fc92a11c ("dmaengine: amd: qdma: Add AMD QDMA driver") Signed-off-by: Lizhi Hou Reviewed-by: Christoph Hellwig --- drivers/dma/amd/qdma/qdma.c | 28 +++++++++++--------------- include/linux/platform_data/amd_qdma.h | 2 ++ 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/dma/amd/qdma/qdma.c b/drivers/dma/amd/qdma/qdma.c index b0a1f3ad851b..4761fa255015 100644 --- a/drivers/dma/amd/qdma/qdma.c +++ b/drivers/dma/amd/qdma/qdma.c @@ -7,9 +7,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -492,18 +492,9 @@ static int qdma_device_verify(struct qdma_device *qdev) static int qdma_device_setup(struct qdma_device *qdev) { - struct device *dev = &qdev->pdev->dev; u32 ring_sz = QDMA_DEFAULT_RING_SIZE; int ret = 0; - while (dev && get_dma_ops(dev)) - dev = dev->parent; - if (!dev) { - qdma_err(qdev, "dma device not found"); - return -EINVAL; - } - set_dma_ops(&qdev->pdev->dev, get_dma_ops(dev)); - ret = qdma_setup_fmap_context(qdev); if (ret) { qdma_err(qdev, "Failed setup fmap context"); @@ -548,11 +539,12 @@ static void qdma_free_queue_resources(struct dma_chan *chan) { struct qdma_queue *queue = to_qdma_queue(chan); struct qdma_device *qdev = queue->qdev; - struct device *dev = qdev->dma_dev.dev; + struct qdma_platdata *pdata; qdma_clear_queue_context(queue); vchan_free_chan_resources(&queue->vchan); - dma_free_coherent(dev, queue->ring_size * QDMA_MM_DESC_SIZE, + pdata = dev_get_platdata(&qdev->pdev->dev); + dma_free_coherent(pdata->dma_dev, queue->ring_size * QDMA_MM_DESC_SIZE, queue->desc_base, queue->dma_desc_base); } @@ -565,6 +557,7 @@ static int qdma_alloc_queue_resources(struct dma_chan *chan) struct qdma_queue *queue = to_qdma_queue(chan); struct qdma_device *qdev = queue->qdev; struct qdma_ctxt_sw_desc desc; + struct qdma_platdata *pdata; size_t size; int ret; @@ -572,8 +565,9 @@ static int qdma_alloc_queue_resources(struct dma_chan *chan) if (ret) return ret; + pdata = dev_get_platdata(&qdev->pdev->dev); size = queue->ring_size * QDMA_MM_DESC_SIZE; - queue->desc_base = dma_alloc_coherent(qdev->dma_dev.dev, size, + queue->desc_base = dma_alloc_coherent(pdata->dma_dev, size, &queue->dma_desc_base, GFP_KERNEL); if (!queue->desc_base) { @@ -588,7 +582,7 @@ static int qdma_alloc_queue_resources(struct dma_chan *chan) if (ret) { qdma_err(qdev, "Failed to setup SW desc ctxt for %s", chan->name); - dma_free_coherent(qdev->dma_dev.dev, size, queue->desc_base, + dma_free_coherent(pdata->dma_dev, size, queue->desc_base, queue->dma_desc_base); return ret; } @@ -948,8 +942,9 @@ static int qdma_init_error_irq(struct qdma_device *qdev) static int qdmam_alloc_qintr_rings(struct qdma_device *qdev) { - u32 ctxt[QDMA_CTXT_REGMAP_LEN]; + struct qdma_platdata *pdata = dev_get_platdata(&qdev->pdev->dev); struct device *dev = &qdev->pdev->dev; + u32 ctxt[QDMA_CTXT_REGMAP_LEN]; struct qdma_intr_ring *ring; struct qdma_ctxt_intr intr_ctxt; u32 vector; @@ -969,7 +964,8 @@ static int qdmam_alloc_qintr_rings(struct qdma_device *qdev) ring->msix_id = qdev->err_irq_idx + i + 1; ring->ridx = i; ring->color = 1; - ring->base = dmam_alloc_coherent(dev, QDMA_INTR_RING_SIZE, + ring->base = dmam_alloc_coherent(pdata->dma_dev, + QDMA_INTR_RING_SIZE, &ring->dev_base, GFP_KERNEL); if (!ring->base) { qdma_err(qdev, "Failed to alloc intr ring %d", i); diff --git a/include/linux/platform_data/amd_qdma.h b/include/linux/platform_data/amd_qdma.h index 576d952f97ed..967a6ef31cf9 100644 --- a/include/linux/platform_data/amd_qdma.h +++ b/include/linux/platform_data/amd_qdma.h @@ -26,11 +26,13 @@ struct dma_slave_map; * @max_mm_channels: Maximum number of MM DMA channels in each direction * @device_map: DMA slave map * @irq_index: The index of first IRQ + * @dma_dev: The device pointer for dma operations */ struct qdma_platdata { u32 max_mm_channels; u32 irq_index; struct dma_slave_map *device_map; + struct device *dma_dev; }; #endif /* _PLATDATA_AMD_QDMA_H */