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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B072.mail.protection.outlook.com (10.167.243.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 10:00:44 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 05:00:42 -0500 From: Basavaraj Natikar To: , CC: , , , , Basavaraj Natikar Subject: [PATCH v8 4/6] dmaengine: ae4dma: Register AE4DMA using pt_dmaengine_register Date: Fri, 25 Oct 2024 15:29:29 +0530 Message-ID: <20241025095931.726018-5-Basavaraj.Natikar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025095931.726018-1-Basavaraj.Natikar@amd.com> References: <20241025095931.726018-1-Basavaraj.Natikar@amd.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B072:EE_|SA0PR12MB4365:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fcc2c38-7ba0-4398-65c3-08dcf4dbe482 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: mFix3BhPwMYzDT9f+nTlblofnSsWq4B2vlBq8TxjLhoAsR5/Nr1Gm0B9peRJeZlbp68cCBabVWkBay+64krj1+RgAnSJJhtn5wIJj/iTvzvpE6jluU2XeAaR6sm2gitIEKtSAAnnTPxwCWS67oq15KWY1EIz+E38uNunULBrj8mlbHuFvTHSB6ow51CluQF/gCXCaBu5yCnZyCzIsirgpGYE8qDFlnpXQs+H8I1T1I4DY7LGrk1Vnl4DAYPvnHW7uXmINbCcEz+BeltYzoagkcBvVCicKfhXKPfhe1f7PljdXJ+fQ3cjJAPyY8TcUnvK9RJW2XGCXJdWolc9lLV2gnWKXfnOeeCKKpSkC5gU8UQQV2novRjbd9IZnY4HQvcUPtFJXZ4Kf8GYmoM0cT0sEAiiq09DE7uckfOZ37pK8w2U/N5JQuCa+cZxASf49cn4EkRSWMmWEb68MdzwfVRFjx3HiGYaRPPt3g/wg6jFnRNQEQNWq5Hy4QaWPbcI4LOJKThsDeKw3zxWS7Fo37xq8Nr58cz5uKcTTMXdQc3F0McSVmS/1CswkQ53bXit/96l3z43+SaSbzlE/xzv0SIH+wRjSjuSrOIuSIPEzEBgyqJi8gyevkOjXm+hAhAZTx+d9pDUYszKZSjC/NXWZN+dqgSi9reDdRe5Q+XsTfy+ZeOBOBjW9E13c3ZwJ9ZLpqmxsvKHPKNrU6+tKvGDv0vk2oZSdAiY/MVr00c7n+92ILJ94JjIqfvIbq+SMtPMy8Lo124G/4bDRLp9t190L+1PjB8Wuw9jCRubWlYSdYcALjStfkXkFyomtqU5f3lm3WoRLSJyR6SgKgfaMVQWe04F7E2FoCv+wxbYoD70Nwb1Dgc2BMfUFrv+RVtxgvD/e274PTpJNXbvkq2dTZeDRczPFlWrkcd/NHttl8G0Ban2L2PN3YSJoNrI272g9p349VOnOtxVtvJFUBL8NY6IvTqlJTzcw1AulCQi/z+EwRns2VU+hwNJ1khpKB735nocsQk2i5eCcCNW/U7Ht/Q8pJe5kCeBRP/XDJlZsT9ejSt9P9M0rehizPyvetOCD323f0h/HbiDFNeKGspadWuAKt3EtWZOfeV8OSffD07tKHJWfFjknpP8wX539xx46IXyjMCwoJdy0zbYi9T2ybN9wr1mwQuhlNr4txAZXGtRvj/9SMeDEkt96mVoBkYBItMN1LISRtz/+e8QOVtmjgXuPsyGclxwTeILog3/Ew6OKqRsrAXKKwTuC8KDFdw1rnaw8x4Q36I5juCfBXgBqsBNu/js5akSZL/803Y1sB/eTUmtSohqcw0cvWGr7rhClPFQNxyzvQILZOFuO4qhpl34atAdhzeDerM5PQ6pBXaRhRhf7gqPBnLfHplEyQa1xgO4ONkAeTbjBPNCA3ENpENWkmUVEQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 10:00:44.7127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6fcc2c38-7ba0-4398-65c3-08dcf4dbe482 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4365 Use the pt_dmaengine_register function to register a AE4DMA DMA engine. Reviewed-by: Raju Rangoju Reviewed-by: Philipp Stanner Signed-off-by: Basavaraj Natikar --- drivers/dma/amd/ae4dma/ae4dma-dev.c | 4 ++ drivers/dma/amd/ae4dma/ae4dma-pci.c | 1 + drivers/dma/amd/ae4dma/ae4dma.h | 2 + drivers/dma/amd/ptdma/ptdma-dmaengine.c | 69 ++++++++++++++++++++++++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/dma/amd/ae4dma/ae4dma-dev.c b/drivers/dma/amd/ae4dma/ae4dma-dev.c index 7cbef9e79f38..cd84b502265e 100644 --- a/drivers/dma/amd/ae4dma/ae4dma-dev.c +++ b/drivers/dma/amd/ae4dma/ae4dma-dev.c @@ -147,5 +147,9 @@ int ae4_core_init(struct ae4_device *ae4) init_completion(&ae4cmd_q->cmp); } + ret = pt_dmaengine_register(pt); + if (ret) + ae4_destroy_work(ae4); + return ret; } diff --git a/drivers/dma/amd/ae4dma/ae4dma-pci.c b/drivers/dma/amd/ae4dma/ae4dma-pci.c index 43d36e9d1efb..aad0dc4294a3 100644 --- a/drivers/dma/amd/ae4dma/ae4dma-pci.c +++ b/drivers/dma/amd/ae4dma/ae4dma-pci.c @@ -98,6 +98,7 @@ static int ae4_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pt = &ae4->pt; pt->dev = dev; + pt->ver = AE4_DMA_VERSION; pt->io_regs = pcim_iomap_table(pdev)[0]; if (!pt->io_regs) { diff --git a/drivers/dma/amd/ae4dma/ae4dma.h b/drivers/dma/amd/ae4dma/ae4dma.h index 92cb8c379c18..265c5d436008 100644 --- a/drivers/dma/amd/ae4dma/ae4dma.h +++ b/drivers/dma/amd/ae4dma/ae4dma.h @@ -35,6 +35,7 @@ #define AE4_Q_SZ 0x20 #define AE4_DMA_VERSION 4 +#define CMD_AE4_DESC_DW0_VAL 2 struct ae4_msix { int msix_count; @@ -55,6 +56,7 @@ struct ae4_cmd_queue { atomic64_t done_cnt; u64 q_cmd_count; u32 dridx; + u32 tail_wi; u32 id; }; diff --git a/drivers/dma/amd/ptdma/ptdma-dmaengine.c b/drivers/dma/amd/ptdma/ptdma-dmaengine.c index e2d4bc8aa1de..35c84ec9608b 100644 --- a/drivers/dma/amd/ptdma/ptdma-dmaengine.c +++ b/drivers/dma/amd/ptdma/ptdma-dmaengine.c @@ -9,6 +9,7 @@ * Author: Gary R Hook */ +#include #include "ptdma.h" #include "../ae4dma/ae4dma.h" #include "../../dmaengine.h" @@ -110,6 +111,53 @@ static struct pt_cmd_queue *pt_get_cmd_queue(struct pt_device *pt, struct pt_dma return cmd_q; } +static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct ae4_cmd_queue *ae4cmd_q) +{ + bool soc = FIELD_GET(DWORD0_SOC, desc->dwouv.dw0); + struct pt_cmd_queue *cmd_q = &ae4cmd_q->cmd_q; + + if (soc) { + desc->dwouv.dw0 |= FIELD_PREP(DWORD0_IOC, desc->dwouv.dw0); + desc->dwouv.dw0 &= ~DWORD0_SOC; + } + + mutex_lock(&ae4cmd_q->cmd_lock); + memcpy(&cmd_q->qbase[ae4cmd_q->tail_wi], desc, sizeof(struct ae4dma_desc)); + ae4cmd_q->q_cmd_count++; + ae4cmd_q->tail_wi = (ae4cmd_q->tail_wi + 1) % CMD_Q_LEN; + writel(ae4cmd_q->tail_wi, cmd_q->reg_control + AE4_WR_IDX_OFF); + mutex_unlock(&ae4cmd_q->cmd_lock); + + wake_up(&ae4cmd_q->q_w); + + return 0; +} + +static int pt_core_perform_passthru_ae4(struct pt_cmd_queue *cmd_q, + struct pt_passthru_engine *pt_engine) +{ + struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct ae4_cmd_queue, cmd_q); + struct ae4dma_desc desc; + + cmd_q->cmd_error = 0; + cmd_q->total_pt_ops++; + memset(&desc, 0, sizeof(desc)); + desc.dwouv.dws.byte0 = CMD_AE4_DESC_DW0_VAL; + + desc.dw1.status = 0; + desc.dw1.err_code = 0; + desc.dw1.desc_id = 0; + + desc.length = pt_engine->src_len; + + desc.src_lo = upper_32_bits(pt_engine->src_dma); + desc.src_hi = lower_32_bits(pt_engine->src_dma); + desc.dst_lo = upper_32_bits(pt_engine->dst_dma); + desc.dst_hi = lower_32_bits(pt_engine->dst_dma); + + return ae4_core_execute_cmd(&desc, ae4cmd_q); +} + static int pt_dma_start_desc(struct pt_dma_desc *desc, struct pt_dma_chan *chan) { struct pt_passthru_engine *pt_engine; @@ -129,7 +177,10 @@ static int pt_dma_start_desc(struct pt_dma_desc *desc, struct pt_dma_chan *chan) pt->tdata.cmd = pt_cmd; /* Execute the command */ - pt_cmd->ret = pt_core_perform_passthru(cmd_q, pt_engine); + if (pt->ver == AE4_DMA_VERSION) + pt_cmd->ret = pt_core_perform_passthru_ae4(cmd_q, pt_engine); + else + pt_cmd->ret = pt_core_perform_passthru(cmd_q, pt_engine); return 0; } @@ -336,6 +387,15 @@ static void pt_issue_pending(struct dma_chan *dma_chan) pt_cmd_callback(desc, 0); } +static void pt_check_status_trans_ae4(struct pt_device *pt, struct pt_cmd_queue *cmd_q) +{ + struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct ae4_cmd_queue, cmd_q); + int i; + + for (i = 0; i < CMD_Q_LEN; i++) + ae4_check_status_error(ae4cmd_q, i); +} + static enum dma_status pt_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *txstate) @@ -346,7 +406,11 @@ pt_tx_status(struct dma_chan *c, dma_cookie_t cookie, cmd_q = pt_get_cmd_queue(pt, chan); - pt_check_status_trans(pt, cmd_q); + if (pt->ver == AE4_DMA_VERSION) + pt_check_status_trans_ae4(pt, cmd_q); + else + pt_check_status_trans(pt, cmd_q); + return dma_cookie_status(c, cookie, txstate); } @@ -512,6 +576,7 @@ int pt_dmaengine_register(struct pt_device *pt) return ret; } +EXPORT_SYMBOL_GPL(pt_dmaengine_register); void pt_dmaengine_unregister(struct pt_device *pt) {