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Thu, 5 Dec 2024 06:59:08 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Thu, 5 Dec 2024 20:28:58 +0530 Message-ID: <20241205145859.2331691-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205145859.2331691-1-mkumard@nvidia.com> References: <20241205145859.2331691-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D6:EE_|PH0PR12MB7470:EE_ X-MS-Office365-Filtering-Correlation-Id: 64ff4009-503f-4f85-173a-08dd153d6860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: DRgflKqmCGvzBa9xhOYFRlTOetr118Y5/Y655HtCgnjCrwpnh4CqOz2YZqAht48dGQP3z8rTWbCVzpahHT9EMd8SeNfcebR6Fiqm8i/r4Ob+Igir7hLAkQaO57iVnGj1WL1Gu9NeXjv0rMqSOi9Ejh4hKwZ22UhnKuri/4pXaNWlPtoPHdSsaiB0arUmENUInmOCYZhfS4BuuXmzfjBsg4KIrYujyNYbQoqD7n/tL6PEddxPnEViC9ykqRkZfJng6T4CBNdTgzv/SqO5jsx1EIc37KiFiePNm0cAKTe5dj3SU3HCHk0Y5znHmwpGRxPlxYAjw50SuvUkkEnSsLarwbjzcB7a0ApCC/81wVJyApxD9c8YkXk2sr9fVQXpPpSGaCmDYSvwDRUFtgleQUCihNAXhH7PuR57fHZ5euPi051LdnsJaB7ATBOjs5dTjm4qR95Mxre9JHcQpHveNwiGtnXcNpkWYSooJKq2A8OpU2fjwVZjUGcNsiL/PfORQKvXycSv8dQK0EEA7FPGm3rPX3wVC8ahvvmOUJS6+c5d1zyCD2WjhLHwZ4GiRPEWz3NZ/HDtOhuNhfEUyM+gsXXNGn/o7RT3+LIWSQaImBlguAW9S6eyNT5yRjy9lZo5zEl1xyY4jRzK0PbnHYzdUOBktUCZyVWCFtQDlZjOdDT3vaxHbN2ggbakwaIrURvq1YrTgylP+YAA7iKc2xcdjfJqJkeT1sp+YWdvK7f6I0IpilSelAbbOFYpBbTokTdgBaR5VzHhThAA6qV5pdXWMHrY+6T9CMJs1xqS9BM8c4nuwUp5ue3AYCIYAZnFIJvXOUBiMLvzrbmZzCs5dlmXPXPpPI4lw3hC0UrfA5WBRpBUApIGh1qsTm+SNQvyfgKcZrSiPQYsGqaVKyGiv/TAxLYEt9oEyTGoMd0LLKub3vv0a/7P5YCoEa5JEARn9p4YknXPKkvtPgXUmtAuOiH5RHm6IVPlZgf+/YBfjtmoIgboNpeIND6Adxxal2c0ZfT3hxmlGedEAsi1c+yEqWjiakYAFnWiSVH6hdAIiVajQkq9T07xlM9Su5Z145GKiJ/0VcYbE/hkT6GajHzg4sujuBngAplR3cWAg+Tkwb+D6UpJGxGV5wUqoKFaUSBymvOiNa7Yc4zZSItNApDIDVVTNYbIgFpol5K/zSJkIxroo+dGJ9UbneV3AK6fLq/iSt7aXVDW5fwmvXSWyF+D53XEjNz/phLXIMzPyYI21dQmuE6iRkr3qK4rnQUC5O66W9b5YRSIzRLKENzCaCDLmrPxnJq09LGhC8CjeHATAztyjOHDRaLicMeRFlD4PBWpQzW4FmBrBf1Yj1t3+ULwlIDUoAzC297J1qJRJIaSXuaFj6/TBXdIcBdEmT3O0mgfVj/aSp73UrP+fbnFuIeeiWgVJhVj0UVv2W7fKE0Nq4k2USvJ8P8Lx6qx+B0/am28qoeQqLFC X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 14:59:24.4482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64ff4009-503f-4f85-173a-08dd153d6860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7470 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D --- .../bindings/dma/nvidia,tegra210-adma.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..8c76c98560c5 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -29,7 +29,24 @@ properties: - const: nvidia,tegra186-adma reg: - maxItems: 1 + description: | + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + oneOf: + - enum: + - page + - global + - items: + - const: page + - const: global interrupts: description: |