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Thu, 12 Dec 2024 04:44:14 -0800 From: Kartik Rajput To: , , , , , , , , Subject: [PATCH] dmaengine: tegra: Return correct DMA status when paused Date: Thu, 12 Dec 2024 18:14:12 +0530 Message-ID: <20241212124412.5650-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001506:EE_|SA1PR12MB7412:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a0fb5b5-1379-4aad-5471-08dd1aaab67e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: JxTA86gh7SU0PYFfJLXagK89zcob7vWUvJkCR3TzdHDHZrVNyHjR1N6fsqPVq/IIuZ3NWWbnAnqZ6VRqnblNWnxWIJaNaq2VPTfTp1h2Qpzdc6zTgXSJNt78VJmiwZC02+h9gv0Dqqdwk84hIyZ3NpYru67rq+0VF2D8T5GQugMkjRTKUAB13FGbFe/5Ufac6pufK/6YV2WBt5zihZd3FYJGh1plRWme/Kl+bj0s3QdXMezhnvVF/53Qcwxys0qamkC7R9I8JiQ5wcEg+ZwVDo2c1tGprNDczF04jrwWpV/PzqsrB9g8l+NwVuTt0e4OIRCGqxDeqnM+jS/dSyhozNX+wQ36szeffaKGXOrogNwI/qyCGRbws6H+Gl0I4v/bcVX3fOo07h3enJYYnx9OmeITCX2Ejxqf4usRGv2sdsjchuq4Loy/OxGbsGIaXBvXPoVNGj8yghEx27dPMjbensXi0TII2bdRygluxp/1Cu9wKr3KV8Ht44LX3eNhBDRFkK/rtu1iGwLa7fEDS3cGDvsQEhGdZEvWHQX4CvKEmK3UAMXb3/7IONiVfnrASFo/mHMK3L9WhSpDAxVEJhewKuWCYnCX2/fHDYCdfkg/xXSBxB+BzeOz3HXzQn4BAfj8gYmSYK8wZ95QJwhVrC/mDEvm3v8uGWNz8q0KrNpSk1U0l/8cbss0snPSPG1NmeNenOVhdiIRU5QiUMp+4gv2xI8M9RW5rMZBuVdmpryFIQk/lmP0cocZ2t2ku/rduIg6FdA5Ov2VihLQ4okmy8QO8qastdBVnXNvUnBnyMMYX7RuI9IC0oQzl39T7sEaa4Ytp0yfKRpgPcKhzq2xyTbhuzhEUUmCLKxO4EFTt0Dqec2w0l2FoLG8e9qFI35U47t5jTdVUnZgtWv7U3LNEuiGhggD5Uv0SguS1w4wX7Qyb+lxKNIjWhdEC+1HZrDlBMaFVd1Jn3su4G0EgruRXXBUbcwqCPntb3OKj61XO2YVSUM+V6msSXayyPRoVurtB2eUyXaasSHM9f+qPlR5gmxHa8mJzmYbHQgdoQVsJ8GjceYIM7vUhdVovg6iziaAXvMzFNWxGncsDpQfd0Anxiz7C8LvjBXwa2kfW5Sb975LpF9q5i+K5SJz5t3xDUnaCENy/U1WPQmyiOd1NqJAzOG/qTZODu3fb0EoRWYSD5O+LOKriESlK4eGTlEMtePT9KOTVjLnbgqiSmmw5210rZN2YRZN155gqMkspKQdQW0Wzz08mXWQmkRMrYCob8op7RznAu/hPtqOjF466dkuf3pAnGf7BTJOi2MwygEJdnW/J2t5amjuNT6kICw3AITxL2ufp2dPER5OrgHpxQm2VTYZSzIohdxep/WAVfGTjkd3W9ip1GzHEnoe5Ps1reXVWM97SckseK8lT7MDbKP8w8uL2qYV9e3IW2JzG5LSokPIxlz1fmKpis/9r6g0dsOir16L X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 12:44:26.3567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a0fb5b5-1379-4aad-5471-08dd1aaab67e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001506.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7412 From: Akhil R Currently, the driver does not return the correct DMA status when a DMA pause is issued by the client drivers. This causes GPCDMA users to assume that DMA is still running, while in reality, the DMA is paused. Return DMA_PAUSED for tx_status() if the channel is paused in the middle of a transfer. Fixes: ee17028009d4 ("dmaengine: tegra: Add tegra gpcdma driver") Cc: stable@vger.kernel.org Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- drivers/dma/tegra186-gpc-dma.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index cacf3757adc2..4d6fe0efa76e 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -231,6 +231,7 @@ struct tegra_dma_channel { bool config_init; char name[30]; enum dma_transfer_direction sid_dir; + enum dma_status status; int id; int irq; int slave_id; @@ -393,6 +394,8 @@ static int tegra_dma_pause(struct tegra_dma_channel *tdc) tegra_dma_dump_chan_regs(tdc); } + tdc->status = DMA_PAUSED; + return ret; } @@ -419,6 +422,8 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc) val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + + tdc->status = DMA_IN_PROGRESS; } static int tegra_dma_device_resume(struct dma_chan *dc) @@ -544,6 +549,7 @@ static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) tegra_dma_sid_free(tdc); tdc->dma_desc = NULL; + tdc->status = DMA_COMPLETE; } static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc, @@ -716,6 +722,7 @@ static int tegra_dma_terminate_all(struct dma_chan *dc) tdc->dma_desc = NULL; } + tdc->status = DMA_COMPLETE; tegra_dma_sid_free(tdc); vchan_get_all_descriptors(&tdc->vc, &head); spin_unlock_irqrestore(&tdc->vc.lock, flags); @@ -769,6 +776,9 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, if (ret == DMA_COMPLETE) return ret; + if (tdc->status == DMA_PAUSED) + ret = DMA_PAUSED; + spin_lock_irqsave(&tdc->vc.lock, flags); vd = vchan_find_desc(&tdc->vc, cookie); if (vd) {