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Fri, 13 Dec 2024 02:39:51 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH v2 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Fri, 13 Dec 2024 16:09:38 +0530 Message-ID: <20241213103939.3851827-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213103939.3851827-1-mkumard@nvidia.com> References: <20241213103939.3851827-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD5:EE_|PH7PR12MB6537:EE_ X-MS-Office365-Filtering-Correlation-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: QbzjfaUt6dLukBcdQXE3uFRIq0uHYchFXNduq+ztan+NtMRYFDijU8OLUoVMB4LtH2It/0la4ypHks4/Ic8BLNiJb4yiQpbuFePRF+gxEVY0H8qaE+2cKLkyN9o4sIvC8nHszfCchk4Kahk9wmgUfMnGzmNjUO2dgh60FV89SUVxOMfNgDtCrqyPxdY3snrn9fA3+SxfOSEVTrwRu8f0IEvsID4zDRSGq6Te3n6eGBvwCLcfRk7ANimRcSbXmmNu/5qyivkEa7Nnvn7UyNQV6AjSR1ApnMtM3sBByps/g7OaHC0WaXfeXpn5cYWcJqz1OJG6TMqAOmOOlzwQAl3jCdsJZ5NhZX/qQRrnv4GpbhS5mrcIrRVEQ+iDSjO5DzxWlhHUSLXXnlWEOnm5qzPIRb8kTAXeRJCeDcpQZnAZomjfR3kaGtTFOQJtNYbNl5YYJv7WnpKAYqKPopq+ec33ZTggUuwcZKfXpspbaZn10m5bXQE7fQjwOspQ0I2YYT6mRpsebRIDA7dEMVe6PVyVYBXwcFxqYYrr6/zn6T39Cv5do6MfLOv6xpXqbew0cSH1jLdfChoOse+koCprKl8cJmYlQdQ/7tkNgSr51eFeFqRuo16UcOyG2EtHHvZumKRRy6MGYVtrzeiXzDwdF6VGlNPyEADISuUqhqNBMJKyCJMdvVwOkjy84DgemWdYtetk2PdQnj2vvCHclOCcReW/aV9awVe26WG3NR+b7pWxWsbahSrtsLs/GK+q2MbJo+ntYMpkAcvmPUuBQ9Kkooz1DeNvccQwDHqzIdOUdTXn/0YyrVpjDYPE5kml+mHd2HrRNEi3qbxCBXXhh3L0hQSTdiUAPCcSPq7Ek8oGQjlPwJ+B0lKIopHzT2ZwNqYI87/PYXlMDUwTn0/IvsRo8ODLTRTWDEu8qmZa9hPljENGcS3rdmNj4V+Ff7o2vxjzw+IeQWPho/KshYnNsk8bJx3bACSArZlOAhEg7jLNVfY66Vux6tmqeUmQrbRUIORv7joYyS/xcjYnKLikUI1lF7E72KENl9wqSdS20vSSnvUgBWTrM8Kz2DemHZkjbW7mm4KN/P3goWgJPtP0GCol02eRrhvtN6XoTDag2DdSuCornTkHPnpxxi9/Xxq9hA70H0slbHWZolZyCIR71tEQ/fluqTTAd30kVrHZQiJxl5CfM1LTUMqFX7Vsf6WauYOdMkb70JvvxGmJTFwkvvJSjf1dg/o9mBEK563BGMpXHofmoAj+pBOPsTVrTMFcPo/T9PznIJ9QSWyKVgLawXGTSbtmDfAJA3VNPSBNi5T4ruHtf8pZpy135xYmdrH2x1mZuorCdWrGEW+h9h7RySuT2ssYDkL68hL3WGE4x6pMKJPpwRA+8dMA0YslsRyoermqUXXzM2L5YFfmwWmqekFvUqN0t3N/gskdNBijVsFkWoMnEYd74GLI9GRgNbOQHXHEddGd X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Dec 2024 10:40:08.3761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6537 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D --- .../bindings/dma/nvidia,tegra210-adma.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..d3f8c269916c 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -13,9 +13,6 @@ description: | maintainers: - Jon Hunter -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -29,7 +26,19 @@ properties: - const: nvidia,tegra186-adma reg: - maxItems: 1 + description: + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 interrupts: description: | @@ -63,6 +72,49 @@ required: - clocks - clock-names +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-adma + then: + properties: + reg: + items: + - description: Full address space range of DMA registers. + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + anyOf: + - properties: + reg: + items: + - description: Full address space range of DMA registers. + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + reg-names: + items: + - const: page + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + - description: Global Page address space range of DMA registers. + reg-names: + items: + - const: page + - const: global + additionalProperties: false examples: