Message ID | 20241216075819.2066772-4-larisa.grigore@oss.nxp.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add eDMAv3 support for S32G2/S32G3 SoCs | expand |
On Mon, Dec 16, 2024 at 09:58:13AM +0200, Larisa Grigore wrote: > Move eDMAv2 related registers to a new structure ’edma2_regs’ to better > support eDMAv3. nit: empty line here. > eDMAv3 registers will be added in the next commit. > > Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/dma/fsl-edma-common.c | 52 ++++++++++++++++++----------------- > drivers/dma/fsl-edma-common.h | 10 +++++-- > drivers/dma/fsl-edma-main.c | 14 ++++++---- > 3 files changed, 42 insertions(+), 34 deletions(-) > > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c > index b7f15ab96855..b132a88dfdec 100644 > --- a/drivers/dma/fsl-edma-common.c > +++ b/drivers/dma/fsl-edma-common.c > @@ -108,14 +108,15 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) > return fsl_edma3_enable_request(fsl_chan); > > if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { > - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); > - edma_writeb(fsl_chan->edma, ch, regs->serq); > + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), > + regs->v2.seei); > + edma_writeb(fsl_chan->edma, ch, regs->v2.serq); > } else { > /* ColdFire is big endian, and accesses natively > * big endian I/O peripherals > */ > - iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); > - iowrite8(ch, regs->serq); > + iowrite8(EDMA_SEEI_SEEI(ch), regs->v2.seei); > + iowrite8(ch, regs->v2.serq); > } > } > > @@ -142,14 +143,15 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) > return fsl_edma3_disable_request(fsl_chan); > > if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { > - edma_writeb(fsl_chan->edma, ch, regs->cerq); > - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); > + edma_writeb(fsl_chan->edma, ch, regs->v2.cerq); > + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), > + regs->v2.ceei); > } else { > /* ColdFire is big endian, and accesses natively > * big endian I/O peripherals > */ > - iowrite8(ch, regs->cerq); > - iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); > + iowrite8(ch, regs->v2.cerq); > + iowrite8(EDMA_CEEI_CEEI(ch), regs->v2.ceei); > } > } > > @@ -880,25 +882,25 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma) > > edma->regs.cr = edma->membase + EDMA_CR; > edma->regs.es = edma->membase + EDMA_ES; > - edma->regs.erql = edma->membase + EDMA_ERQ; > - edma->regs.eeil = edma->membase + EDMA_EEI; > - > - edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); > - edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); > - edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); > - edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); > - edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); > - edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); > - edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); > - edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); > - edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); > - edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); > + edma->regs.v2.erql = edma->membase + EDMA_ERQ; > + edma->regs.v2.eeil = edma->membase + EDMA_EEI; > + > + edma->regs.v2.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); > + edma->regs.v2.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); > + edma->regs.v2.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); > + edma->regs.v2.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); > + edma->regs.v2.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); > + edma->regs.v2.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); > + edma->regs.v2.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); > + edma->regs.v2.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); > + edma->regs.v2.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); > + edma->regs.v2.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); > > if (is64) { > - edma->regs.erqh = edma->membase + EDMA64_ERQH; > - edma->regs.eeih = edma->membase + EDMA64_EEIH; > - edma->regs.errh = edma->membase + EDMA64_ERRH; > - edma->regs.inth = edma->membase + EDMA64_INTH; > + edma->regs.v2.erqh = edma->membase + EDMA64_ERQH; > + edma->regs.v2.eeih = edma->membase + EDMA64_EEIH; > + edma->regs.v2.errh = edma->membase + EDMA64_ERRH; > + edma->regs.v2.inth = edma->membase + EDMA64_INTH; > } > } > > diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h > index ce37e1ee9c46..f1362daaa347 100644 > --- a/drivers/dma/fsl-edma-common.h > +++ b/drivers/dma/fsl-edma-common.h > @@ -120,9 +120,7 @@ struct fsl_edma3_ch_reg { > /* > * These are iomem pointers, for both v32 and v64. > */ > -struct edma_regs { > - void __iomem *cr; > - void __iomem *es; > +struct edma2_regs { > void __iomem *erqh; > void __iomem *erql; /* aka erq on v32 */ > void __iomem *eeih; > @@ -141,6 +139,12 @@ struct edma_regs { > void __iomem *errl; > }; > > +struct edma_regs { > + void __iomem *cr; > + void __iomem *es; > + struct edma2_regs v2; > +}; > + > struct fsl_edma_sw_tcd { > dma_addr_t ptcd; > void *vtcd; > diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c > index 9873cce00c68..0b89c31bf38c 100644 > --- a/drivers/dma/fsl-edma-main.c > +++ b/drivers/dma/fsl-edma-main.c > @@ -36,13 +36,14 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) > unsigned int intr, ch; > struct edma_regs *regs = &fsl_edma->regs; > > - intr = edma_readl(fsl_edma, regs->intl); > + intr = edma_readl(fsl_edma, regs->v2.intl); > if (!intr) > return IRQ_NONE; > > for (ch = 0; ch < fsl_edma->n_chans; ch++) { > if (intr & (0x1 << ch)) { > - edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); > + edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), > + regs->v2.cint); > fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); > } > } > @@ -78,14 +79,15 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) > unsigned int err, ch; > struct edma_regs *regs = &fsl_edma->regs; > > - err = edma_readl(fsl_edma, regs->errl); > + err = edma_readl(fsl_edma, regs->v2.errl); > if (!err) > return IRQ_NONE; > > for (ch = 0; ch < fsl_edma->n_chans; ch++) { > if (err & (0x1 << ch)) { > fsl_edma_disable_request(&fsl_edma->chans[ch]); > - edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); > + edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), > + regs->v2.cerr); > fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); > } > } > @@ -216,7 +218,7 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma > { > int ret; > > - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); > + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); > > fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); > if (fsl_edma->txirq < 0) > @@ -281,7 +283,7 @@ fsl_edma2_irq_init(struct platform_device *pdev, > int i, ret, irq; > int count; > > - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); > + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); > > count = platform_irq_count(pdev); > dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); > -- > 2.47.0 >
On 12/16/2024 6:17 PM, Frank Li wrote: > On Mon, Dec 16, 2024 at 09:58:13AM +0200, Larisa Grigore wrote: >> Move eDMAv2 related registers to a new structure ’edma2_regs’ to better >> support eDMAv3. > > nit: empty line here. > Thanks for your review Frank! I will fix it in V2. >> eDMAv3 registers will be added in the next commit. >> >> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > >> --- >> drivers/dma/fsl-edma-common.c | 52 ++++++++++++++++++----------------- >> drivers/dma/fsl-edma-common.h | 10 +++++-- >> drivers/dma/fsl-edma-main.c | 14 ++++++---- >> 3 files changed, 42 insertions(+), 34 deletions(-) >> >> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c >> index b7f15ab96855..b132a88dfdec 100644 >> --- a/drivers/dma/fsl-edma-common.c >> +++ b/drivers/dma/fsl-edma-common.c >> @@ -108,14 +108,15 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) >> return fsl_edma3_enable_request(fsl_chan); >> >> if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { >> - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); >> - edma_writeb(fsl_chan->edma, ch, regs->serq); >> + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), >> + regs->v2.seei); >> + edma_writeb(fsl_chan->edma, ch, regs->v2.serq); >> } else { >> /* ColdFire is big endian, and accesses natively >> * big endian I/O peripherals >> */ >> - iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); >> - iowrite8(ch, regs->serq); >> + iowrite8(EDMA_SEEI_SEEI(ch), regs->v2.seei); >> + iowrite8(ch, regs->v2.serq); >> } >> } >> >> @@ -142,14 +143,15 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) >> return fsl_edma3_disable_request(fsl_chan); >> >> if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { >> - edma_writeb(fsl_chan->edma, ch, regs->cerq); >> - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); >> + edma_writeb(fsl_chan->edma, ch, regs->v2.cerq); >> + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), >> + regs->v2.ceei); >> } else { >> /* ColdFire is big endian, and accesses natively >> * big endian I/O peripherals >> */ >> - iowrite8(ch, regs->cerq); >> - iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); >> + iowrite8(ch, regs->v2.cerq); >> + iowrite8(EDMA_CEEI_CEEI(ch), regs->v2.ceei); >> } >> } >> >> @@ -880,25 +882,25 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma) >> >> edma->regs.cr = edma->membase + EDMA_CR; >> edma->regs.es = edma->membase + EDMA_ES; >> - edma->regs.erql = edma->membase + EDMA_ERQ; >> - edma->regs.eeil = edma->membase + EDMA_EEI; >> - >> - edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); >> - edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); >> - edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); >> - edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); >> - edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); >> - edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); >> - edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); >> - edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); >> - edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); >> - edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); >> + edma->regs.v2.erql = edma->membase + EDMA_ERQ; >> + edma->regs.v2.eeil = edma->membase + EDMA_EEI; >> + >> + edma->regs.v2.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); >> + edma->regs.v2.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); >> + edma->regs.v2.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); >> + edma->regs.v2.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); >> + edma->regs.v2.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); >> + edma->regs.v2.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); >> + edma->regs.v2.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); >> + edma->regs.v2.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); >> + edma->regs.v2.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); >> + edma->regs.v2.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); >> >> if (is64) { >> - edma->regs.erqh = edma->membase + EDMA64_ERQH; >> - edma->regs.eeih = edma->membase + EDMA64_EEIH; >> - edma->regs.errh = edma->membase + EDMA64_ERRH; >> - edma->regs.inth = edma->membase + EDMA64_INTH; >> + edma->regs.v2.erqh = edma->membase + EDMA64_ERQH; >> + edma->regs.v2.eeih = edma->membase + EDMA64_EEIH; >> + edma->regs.v2.errh = edma->membase + EDMA64_ERRH; >> + edma->regs.v2.inth = edma->membase + EDMA64_INTH; >> } >> } >> >> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h >> index ce37e1ee9c46..f1362daaa347 100644 >> --- a/drivers/dma/fsl-edma-common.h >> +++ b/drivers/dma/fsl-edma-common.h >> @@ -120,9 +120,7 @@ struct fsl_edma3_ch_reg { >> /* >> * These are iomem pointers, for both v32 and v64. >> */ >> -struct edma_regs { >> - void __iomem *cr; >> - void __iomem *es; >> +struct edma2_regs { >> void __iomem *erqh; >> void __iomem *erql; /* aka erq on v32 */ >> void __iomem *eeih; >> @@ -141,6 +139,12 @@ struct edma_regs { >> void __iomem *errl; >> }; >> >> +struct edma_regs { >> + void __iomem *cr; >> + void __iomem *es; >> + struct edma2_regs v2; >> +}; >> + >> struct fsl_edma_sw_tcd { >> dma_addr_t ptcd; >> void *vtcd; >> diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c >> index 9873cce00c68..0b89c31bf38c 100644 >> --- a/drivers/dma/fsl-edma-main.c >> +++ b/drivers/dma/fsl-edma-main.c >> @@ -36,13 +36,14 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) >> unsigned int intr, ch; >> struct edma_regs *regs = &fsl_edma->regs; >> >> - intr = edma_readl(fsl_edma, regs->intl); >> + intr = edma_readl(fsl_edma, regs->v2.intl); >> if (!intr) >> return IRQ_NONE; >> >> for (ch = 0; ch < fsl_edma->n_chans; ch++) { >> if (intr & (0x1 << ch)) { >> - edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); >> + edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), >> + regs->v2.cint); >> fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); >> } >> } >> @@ -78,14 +79,15 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) >> unsigned int err, ch; >> struct edma_regs *regs = &fsl_edma->regs; >> >> - err = edma_readl(fsl_edma, regs->errl); >> + err = edma_readl(fsl_edma, regs->v2.errl); >> if (!err) >> return IRQ_NONE; >> >> for (ch = 0; ch < fsl_edma->n_chans; ch++) { >> if (err & (0x1 << ch)) { >> fsl_edma_disable_request(&fsl_edma->chans[ch]); >> - edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); >> + edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), >> + regs->v2.cerr); >> fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); >> } >> } >> @@ -216,7 +218,7 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma >> { >> int ret; >> >> - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); >> + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); >> >> fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); >> if (fsl_edma->txirq < 0) >> @@ -281,7 +283,7 @@ fsl_edma2_irq_init(struct platform_device *pdev, >> int i, ret, irq; >> int count; >> >> - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); >> + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); >> >> count = platform_irq_count(pdev); >> dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); >> -- >> 2.47.0 >> Best regards, Larisa
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index b7f15ab96855..b132a88dfdec 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -108,14 +108,15 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) return fsl_edma3_enable_request(fsl_chan); if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); - edma_writeb(fsl_chan->edma, ch, regs->serq); + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), + regs->v2.seei); + edma_writeb(fsl_chan->edma, ch, regs->v2.serq); } else { /* ColdFire is big endian, and accesses natively * big endian I/O peripherals */ - iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); - iowrite8(ch, regs->serq); + iowrite8(EDMA_SEEI_SEEI(ch), regs->v2.seei); + iowrite8(ch, regs->v2.serq); } } @@ -142,14 +143,15 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) return fsl_edma3_disable_request(fsl_chan); if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { - edma_writeb(fsl_chan->edma, ch, regs->cerq); - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); + edma_writeb(fsl_chan->edma, ch, regs->v2.cerq); + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), + regs->v2.ceei); } else { /* ColdFire is big endian, and accesses natively * big endian I/O peripherals */ - iowrite8(ch, regs->cerq); - iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); + iowrite8(ch, regs->v2.cerq); + iowrite8(EDMA_CEEI_CEEI(ch), regs->v2.ceei); } } @@ -880,25 +882,25 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma) edma->regs.cr = edma->membase + EDMA_CR; edma->regs.es = edma->membase + EDMA_ES; - edma->regs.erql = edma->membase + EDMA_ERQ; - edma->regs.eeil = edma->membase + EDMA_EEI; - - edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); - edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); - edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); - edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); - edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); - edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); - edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); - edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); - edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); - edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); + edma->regs.v2.erql = edma->membase + EDMA_ERQ; + edma->regs.v2.eeil = edma->membase + EDMA_EEI; + + edma->regs.v2.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); + edma->regs.v2.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); + edma->regs.v2.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); + edma->regs.v2.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); + edma->regs.v2.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); + edma->regs.v2.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); + edma->regs.v2.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); + edma->regs.v2.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); + edma->regs.v2.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); + edma->regs.v2.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); if (is64) { - edma->regs.erqh = edma->membase + EDMA64_ERQH; - edma->regs.eeih = edma->membase + EDMA64_EEIH; - edma->regs.errh = edma->membase + EDMA64_ERRH; - edma->regs.inth = edma->membase + EDMA64_INTH; + edma->regs.v2.erqh = edma->membase + EDMA64_ERQH; + edma->regs.v2.eeih = edma->membase + EDMA64_EEIH; + edma->regs.v2.errh = edma->membase + EDMA64_ERRH; + edma->regs.v2.inth = edma->membase + EDMA64_INTH; } } diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index ce37e1ee9c46..f1362daaa347 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -120,9 +120,7 @@ struct fsl_edma3_ch_reg { /* * These are iomem pointers, for both v32 and v64. */ -struct edma_regs { - void __iomem *cr; - void __iomem *es; +struct edma2_regs { void __iomem *erqh; void __iomem *erql; /* aka erq on v32 */ void __iomem *eeih; @@ -141,6 +139,12 @@ struct edma_regs { void __iomem *errl; }; +struct edma_regs { + void __iomem *cr; + void __iomem *es; + struct edma2_regs v2; +}; + struct fsl_edma_sw_tcd { dma_addr_t ptcd; void *vtcd; diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 9873cce00c68..0b89c31bf38c 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -36,13 +36,14 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) unsigned int intr, ch; struct edma_regs *regs = &fsl_edma->regs; - intr = edma_readl(fsl_edma, regs->intl); + intr = edma_readl(fsl_edma, regs->v2.intl); if (!intr) return IRQ_NONE; for (ch = 0; ch < fsl_edma->n_chans; ch++) { if (intr & (0x1 << ch)) { - edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); + edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), + regs->v2.cint); fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); } } @@ -78,14 +79,15 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) unsigned int err, ch; struct edma_regs *regs = &fsl_edma->regs; - err = edma_readl(fsl_edma, regs->errl); + err = edma_readl(fsl_edma, regs->v2.errl); if (!err) return IRQ_NONE; for (ch = 0; ch < fsl_edma->n_chans; ch++) { if (err & (0x1 << ch)) { fsl_edma_disable_request(&fsl_edma->chans[ch]); - edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); + edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), + regs->v2.cerr); fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); } } @@ -216,7 +218,7 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma { int ret; - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); if (fsl_edma->txirq < 0) @@ -281,7 +283,7 @@ fsl_edma2_irq_init(struct platform_device *pdev, int i, ret, irq; int count; - edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); + edma_writel(fsl_edma, ~0, fsl_edma->regs.v2.intl); count = platform_irq_count(pdev); dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
Move eDMAv2 related registers to a new structure ’edma2_regs’ to better support eDMAv3. eDMAv3 registers will be added in the next commit. Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> --- drivers/dma/fsl-edma-common.c | 52 ++++++++++++++++++----------------- drivers/dma/fsl-edma-common.h | 10 +++++-- drivers/dma/fsl-edma-main.c | 14 ++++++---- 3 files changed, 42 insertions(+), 34 deletions(-)