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Mon, 16 Dec 2024 23:44:11 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , "Mohan Kumar D" Subject: [PATCH v2 RESEND 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Tue, 17 Dec 2024 13:13:57 +0530 Message-ID: <20241217074358.340180-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241217074358.340180-1-mkumard@nvidia.com> References: <20241217074358.340180-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C9:EE_|MN0PR12MB6002:EE_ X-MS-Office365-Filtering-Correlation-Id: 745f9210-6303-48f5-ff94-08dd1e6e9e52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: MDYo3zgcJwKAAM4m8uhshhsy71TwKrAmMQl1JW2lALIBV3XqNbYPe/mCaToSPzJL683qAstAmTUcaO7xKLIw7X/+jQWoUOEpYmWCWbMhlDHYlF7qr/S2m08vYvsaJXw1KfAtIL8f4HevmuF5SJGzke5xVQIW0r731qyLncdPeYiwQ8TbTKaKt0xPJIeRH7PuslYmEikqe8TrPmhcs4NT7X8E0B3DGj3sV0Spx4REmrcFmfZykpgomZNEPL3lqKbwg1+yrCCShzGuStqfQCM1iO/jP8231mcm47bis3fCM7WoBNqGjtQTgCenOwzqqLmGaLzrkD63wV0HHCeVSgkkbgM3wEOVBkFrGYkfM7g58TVWBq3832GLTjChXGIYTRNIlyluZ0eOKyHE3ZCtHUHCKb622wW4JLmkpkCgL4aEX/bFQuOGU6rHYyB69pc9Fy5HOZlze/cgbqKnL87YydRQSLBgfQs7Rii1+en0VelCWR2dThsOR8QGWkv9q5TwF6OZ7t6L0tahmL38YMT4KsXkq3OXwac7Trpd3Ctmt6ZyJnz2bXIUDVF5d2pj1u6SviaTkr87JMO4QSNKAcrpevDj9jFzLCJH8PYHPnchuqirfTsbFwDTIwA/RQNbOEwfuXZvMT6Hi9ORGaZ8+G023q2rqjxvbpMd5yI5MWzOQIUWffhJWOeDiI5ZPwbSkEcqiMgxHA2zHhOSpRE3dNawKvRfpZbtJi/i2r7ff183XDbZBQFSB5m6iG7bE8D/DwPIgbDzyBXnTltx+EIWFXXooWWKygSCR5J5GKw6HnWtSoUIbHP8OJxV+TbdSW2ttsiFrRCsDRkTaU6yzc5o0e6kXuxI19bagDMZRQWB0QLiU1tNQkffWXy9+E5s6RZZ1Yt18d9a7JH1ry/zS4CX3xH9srvn6E5QobQAVfS03bpSY1Mo0huR1UmR3U/+o9QsEtEYeUkXA3HdqQw+1e8HpS8o5h0Ru6t8ySS6VSpTf2mdZI8hTcMUd99ISZbjtQzQ6T2GhHSQQ5fGNbz72jeS55mAhmBQ6fMOPqt9OcEdkc+l5Bnb6Ybv0KexUdH0Xl9vHAvqYJ6/ibLhaD5Z4uExKVnCydw5Ol7LAxne0cRE3St8A9r0jk5B6Ie8M6pF7vj5ixfzw52EMB4mdzKxA1BZU3+wQRxpwqcIpZcG8GzqK8TB1BRG8mM3l87qA44x6+bbkp4o3M4qr9izxAWIWYpqogEw7Wh3MIsDwWhWXNOX5qO9EJwleHppPv79LXT6eQJUX+ICm2yOpnO1kGYG7qxyTGCPAd5oz12+Y21FIINWCoorreBYkRDCMO0zFE0bWHlEyuT3yWhdrns2E/OZbrYLEQrdAM3q5iMSxiRZp1phrxbpeb2K8EupIi0sBQL25dt9kpLu/9eG4DWTnOWTNSFCD9LDQVSJORrJ9BrK3XWeAtvf/KILEfkTPBPR+K6G/LGrOwam7RlqkeXSBLYiv8jNAVpcN3dtZF2gPSSGEjg/iZxXuNZQ/UE= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 07:44:20.7797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 745f9210-6303-48f5-ff94-08dd1e6e9e52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6002 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D Acked-by: Conor Dooley --- .../bindings/dma/nvidia,tegra210-adma.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..d3f8c269916c 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -13,9 +13,6 @@ description: | maintainers: - Jon Hunter -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -29,7 +26,19 @@ properties: - const: nvidia,tegra186-adma reg: - maxItems: 1 + description: + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 interrupts: description: | @@ -63,6 +72,49 @@ required: - clocks - clock-names +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-adma + then: + properties: + reg: + items: + - description: Full address space range of DMA registers. + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + anyOf: + - properties: + reg: + items: + - description: Full address space range of DMA registers. + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + reg-names: + items: + - const: page + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + - description: Global Page address space range of DMA registers. + reg-names: + items: + - const: page + - const: global + additionalProperties: false examples: