From patchwork Thu Dec 19 09:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Larisa Ileana Grigore X-Patchwork-Id: 13914866 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2052.outbound.protection.outlook.com [40.107.22.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF423223719; Thu, 19 Dec 2024 09:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.22.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734600070; cv=fail; b=Oc/4EfDw9UtN9MR6N8XEEmc/TLNzGllmSgB+ErM4NsVlIEBqJPYa7TcbdWNVfFQxZX3ZYtNN3LAFL8gbpfwuwnDcc331tpbw5BQfjIx75w1uq11XF9iM9go75wyROts16UUN2SqiWDofKB+6GKOkd25ChhcOXiR4AEPoraFV9eo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734600070; c=relaxed/simple; bh=HmGCBiXoSrLxJwMM4N4YHRHB1wg19cbqt0DXJEaz1TQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=EdnoWWHtatGGkWfMOijSdwzz7D21EMK/fkuC4WZisHpdLyv2FRCEzOjepuquM+Bs4jQ2tUsVJbrTKJNd7shNRIP4Gn6+9CSwxrfLYWOfxZ/n1PR5/5MfC6mm/EkikunvtxgpzuCg5qApJ4Sn4/mT9g80s1qi67PKFVHx9vpY+CI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=s0mWOSwi; arc=fail smtp.client-ip=40.107.22.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="s0mWOSwi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WsN3tEoaj+pAxZAcSiV/xm1vT9/7FxP3rOl4Kp/M+5P4pEiWNbt5XHicd2O4fZEZiDzQp4+Th+QL7dPeGLsml5yR3lynoszhcqdebePTu4Ply0VA3fP/KPzwaghr/KaMOAzNCfEGoxUf8/y0tybSpI0YE7O72QEF26MrwMJe4JB1xSCIHcUbwbBJFXdwGx0G+N4eO+hkY8C688QCnISf1gl6WlGpDWxY4jSqg4fr4bJ2OTYlo3mDv90lpBkm+eJClKK5kklOpx0avxQBgEFGTpkxdGWv3EjuO8BccWID/WHUq5APMllpUVYchkEh4EMFD58sV4Gs8QwWqu/Ty1i9JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Mc/TtVZP9h6Q5W2GpYNktrmwxyrCTzOZfm5JA7UiZkg=; b=SKRfYFfq4S1nidjF4yvtfYBQBEmIhiGmGDFkG+cJuqA6/wvOXkn4lg/YgltLPrzyrra7bMdd7L48FF/43CJIw5vGGE/dK134Gb8bhHV7Vi06L3sR3sifGYqAZgVFINWfEypjuGrDBEuX4ETeBKbZO1Q15Kl7A9I+WtfUCHhUPr3LyO4uLJPG0Sz5Qy6MQBCvqpN9i40d4pn1u/jJqo+BY/WM5wfAOZLUWNCsp9hGJNr4CbQknDTqt3hnbLFoMACUl/xFpzxOF3IblSEi/mV/2Yr+X7p8hcZE+LhLj9/B1bh/Bucf6vSTutzX1K8W30l3z2FnEgJcMLz94W8A0gxG4g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Mc/TtVZP9h6Q5W2GpYNktrmwxyrCTzOZfm5JA7UiZkg=; b=s0mWOSwikFlMkLwCF+/bXt3OXRm95O5ViObneGw58OwXSJPf8eyovmbmlBeGDGki8hPF71Yo0BifAa0uVSka1YuT2jEeJrpHgAs8egdmKwsPy/3b5v3BF9s2cvOEUw/L2l3CcohblzrgU/YikgKILx2KxMxiFef6aZPcu+J6R4peF4ZpVuNWfbQKPta4Tn9PHL+VP6BUYoMHO2N6aw9WijkS+wi2lFU26dCd4CBHX/6cN903UeHDOEOiZddKLjNZuHN2jCx9og+C1TUKkoMvPHZb9GtkoJS579V8+t0Al03lzQ32yLCp/fvjonYLsZn8Z9NQ2ycIG8RuC6MBgAPP3g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from AS4PR04MB9550.eurprd04.prod.outlook.com (2603:10a6:20b:4f9::17) by VI1PR04MB9834.eurprd04.prod.outlook.com (2603:10a6:800:1d8::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8272.14; Thu, 19 Dec 2024 09:21:00 +0000 Received: from AS4PR04MB9550.eurprd04.prod.outlook.com ([fe80::e28d:10f8:289:baf7]) by AS4PR04MB9550.eurprd04.prod.outlook.com ([fe80::e28d:10f8:289:baf7%6]) with mapi id 15.20.8251.015; Thu, 19 Dec 2024 09:21:00 +0000 From: Larisa Grigore To: Frank Li , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peng Fan Cc: imx@lists.linux.dev, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, s32@nxp.com, Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Larisa Grigore , Ciprian Marian Costea Subject: [PATCH v2 4/6] dmaengine: fsl-edma: add support for S32G based platforms Date: Thu, 19 Dec 2024 11:18:44 +0200 Message-ID: <20241219092045.1161182-5-larisa.grigore@oss.nxp.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241219092045.1161182-1-larisa.grigore@oss.nxp.com> References: <20241219092045.1161182-1-larisa.grigore@oss.nxp.com> X-ClientProxiedBy: AM0PR02CA0200.eurprd02.prod.outlook.com (2603:10a6:20b:28f::7) To AS4PR04MB9550.eurprd04.prod.outlook.com (2603:10a6:20b:4f9::17) Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS4PR04MB9550:EE_|VI1PR04MB9834:EE_ X-MS-Office365-Filtering-Correlation-Id: 96e79252-d310-4aaf-9f19-08dd200e73fe X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?rShANalS7KRZx5lwg0bepEb28qEweYe?= =?utf-8?q?Q4KefJ2tqvazbJWr1SNHNWPtYQOqhEDIQmpLbvoOCuTd8VWPbi54tndYDBe7F1N/G?= =?utf-8?q?nUUKCktEFi0gJmQ12fpxvCnITFfgIwUOsvlhhJ9MW9JSaZsbrD8WvOMVoucG7Tx+T?= =?utf-8?q?ejgc631X6yItsvM6Q20/eaTCOjOxwXMdf5+dPq13mFq778LL1veeIkXp2v4tiuU5x?= =?utf-8?q?65JwwT7l4Mjmf7K4EDewbmzj+0JkzXtyOzhPiGUmdrx12ZjbwDqbNXIAREJE5zYLI?= =?utf-8?q?jhz9JO7Wup8E+etXEu1MhqfWBtgrdVwe8+c87hGK0taHILdm2OBBTswomw+35UWYF?= =?utf-8?q?RyW87RBcKhn8PSwM38ZzbKPdr/WEKRufrpFQ6fsPGFZ7aCuGSESymRmZTAq3yAS1a?= =?utf-8?q?n5c6cf1Ua68mLoh0SDT9cmK1uA/v5m1yYXQF1uClPOm2Q3mds+AN49wBra0f57JS5?= =?utf-8?q?35pOv1GGpj+dfm9Vb0l56Kq9V6rXtVmOqUEiI3Ke3fidgsPUmGHvXi6bza/mD2pJq?= =?utf-8?q?BM+mFiKZNAh0FtO8LK6iyf6M42sVL7kczEHeYpHOIpqI9NN+TcD3WTap9Rd7+YVYZ?= =?utf-8?q?3ygrg7oYbmd8QcWnMyGm2nscVmhNomeA2Uz7Kb5Fh+kIOwRNTfiG03fQedErKALL4?= =?utf-8?q?l3JnxGkd1SUkXLPK+OqLy2KX41TO/xk2bhbnr2nOas9rScKHDTI1Njl3BzHH/UT8q?= =?utf-8?q?Gc8F4vXfys7EjScHBBrW6KQfVK91JwKJlFCXShIWAK1klSaRqVFM6rzlKE/FUMbER?= =?utf-8?q?hHlcJ9MXkn8X42wPuQ3FDXW8v2ERFEgir+L03AmQxQRB704ljKTed2XaVmKFum7OP?= =?utf-8?q?FzJS6KWX25iZpsbt2hXgbJqdJ9+uycEy4F2HxwyCfibN64HYVgR6KSvBBzt+CKfNm?= =?utf-8?q?m5M2v2ZFJtYb8m9sPMcJF37CLcNVJjbLXm11kfN4LSWyzOEwZ9snX0hHjYYk8qWzA?= =?utf-8?q?lotWfbwcK8KE6Vl0Ph3VSm4mTrwEewI3j3MhZ51EXRmp/3/+mY3y8G+2WrEhGALFU?= =?utf-8?q?VcIxUUkLbuxVxkH4g4Chpo6Kj1YAN70xEoYNGNHqYLPL2YtjnVdLyBhEnKqNXtD3V?= =?utf-8?q?aXGsQjaFLg1UnHslK1pyuDfFy0haOp9rw7D3gqc5VlGoTWxNPu2mhVgJRmkBP8E93?= =?utf-8?q?h83OdsROm4mHo8eMtMnJPvBY8K0A1L0NFPuq7jyhn4n5MQ+9vNsrV9sajPSxFS48U?= =?utf-8?q?HJ4n7m968MIRFb79a3demtg981fBvt1EwKA4FZoFlF8cWahndn8PH0iPIi/Epl8oh?= =?utf-8?q?RvmNHdOLh0EMMsNPHzjY3EBOFbxrX+TDaRPMarbZUcKHJabIIdzRobQrpRzxP+PVn?= =?utf-8?q?qWzwShIk9t9f?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS4PR04MB9550.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?nrVS/wwG7o0fg6a/UIDtjojqfGlK?= =?utf-8?q?7r3BBQ4Bij//Jnu4omHCx+lSj2b9WcBHUB4aHdW0qYgEZZrlW7ZFatGC4qWktp1PA?= =?utf-8?q?kqhlugatg5HpBsGmBGM90zu4eu8OmtdS9AoZzzpSSs0DU+tHGrReJ6QNOCMK4+rU1?= =?utf-8?q?O44zAAPvG59Pei6F/R3PVtfo3/3Zp7U3maGgxpODh/SAfgqTiP5Ti1mUz3++cJtIC?= =?utf-8?q?PKatrL0/3cmTRrpC2pao98sueky94QSGxVPuulTyDGWX08GytQ7H9qbq2b0QOcjxK?= =?utf-8?q?slB0sEW2IbJqnpDgoWBTJmMJ5Eo0+QiDOGAABMzo7g5oLkPjZVfO/kjRUKWE63Yd/?= =?utf-8?q?8+wrQDbrymTyOqY5e+PTENMweL+T2578dwlVIzfO5Tdgzi8e2/yftD7b4Ct3CqB7H?= =?utf-8?q?qFxjBBihpELoUtuDvaYHERjyEdNvKal5N5mZcm3MhQGqGS/1/uiLFPPe0SqJguMSR?= =?utf-8?q?0RrFYK1kUx8aCwCpDxP7O5HtKDi2CYiNsgSQag128qQ7DNYXBLlVj+x+/z7CCWgfz?= =?utf-8?q?yztrOtslUFpf4f2TM9yKbdo/kt1l6kVOilLHAt8s/NgR/eWyRoX7U7emU/NumnX0N?= =?utf-8?q?2S2gDhurl1WrOUyQxl3r6i4PEgOdnnEkbjh1+1U5HlV0uctdIs3w9c2VIZBHmDrr9?= =?utf-8?q?c74Ov88PvFyQH/+PxlGp0FqFD/hAn353POV2XQNGglVOCG9YWOiHciV1hkM7EQV5i?= =?utf-8?q?C6+uVq+6qwjZfTIpoEkSsniIBo+v96/iIWNZhJpyurdkTATMOtLH5cFk6dXefA29g?= =?utf-8?q?ob/5EbghjwOQ5pFhAlUOrk5x5sYvaUUSFfVbM9bxMcXbymZL1t6aiE1yvLWaUOUpG?= =?utf-8?q?Vi90d1uHjq+MPtRPy1WRcKwISKLFofYXKx87zjeadINdQnX84wb+3c3iuzTOiDAqA?= =?utf-8?q?rkk2wmSHdtheBIRwCiqDoERHvsRxpEahCQU18qr5PinY8NPK3dFoI+y2M2fHkpRIa?= =?utf-8?q?PSEePAjABdSiPZT3s2i9ZaRNI9LgrZb0Xp3jEgVzb6Wh4y7BSHJbBR/LrbfRySImd?= =?utf-8?q?CsS/qSX29xL8Ie6Gp5zdDvUjLa6GFD1mdIl/84yUELOpNAhQaGff9uhXHC5FJfAdq?= =?utf-8?q?cIiV5HNDmI37o6onKhq2SwY6GN1rieO3Jmq8A+dYDIQGux74XaTrpDtLqBcyl2Oef?= =?utf-8?q?Ft+m+CfD5GH0SzhmHKimX7rKjX+3e5GgbNF4Fy3aSP4zA1fxe/4Pyi8wwW4ZxQsZ3?= =?utf-8?q?ZykE94a7kE3Cw2WgA+olmz46LDwn5AV7FXs6Gx+qdomyW71JuRvt34kkO8WkCv0KG?= =?utf-8?q?NB9C6TETPq2AE4CQ9gT/uy+xzVljgmPvvE7E0OHJK8VJAHcEnUxpEYEfRUlpXk3o3?= =?utf-8?q?9fI51ZoeeZu+vytWHKr3r9+pa8lNpZQXRHfLabaDow3NEKJMZoNdKrqoAy8NUAAPB?= =?utf-8?q?avSoeZtst/9Z5l2L/m+7wfu1Id/M2JjjiLZYkfLjIr2l33lmps3+dbsIAHZg7CL0e?= =?utf-8?q?O03BXs8xMaUUCpe0PF0fCzTNhhIKbITimsrKV7L6mrCNk/1rixHSVw+grk5Dwarl6?= =?utf-8?q?URGb9IxrGsIr?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 96e79252-d310-4aaf-9f19-08dd200e73fe X-MS-Exchange-CrossTenant-AuthSource: AS4PR04MB9550.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2024 09:21:00.5320 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /uoFSXx5Tq/qnyrmwlfjKMV17i4JXntRA4cjor6qFY97SlSk2b1b5MGkDuBzwJEV3QF58QDCMXCjALGfhwbEsg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB9834 S32G2/S32G3 includes two system eDMA instances based on v3 version, each of them integrated with two DMAMUX blocks. Another particularity of these SoCs is that the interrupts are shared between channels as follows: - DMA Channels 0-15 share the 'tx-0-15' interrupt - DMA Channels 16-31 share the 'tx-16-31' interrupt - all channels share the 'err' interrupt Signed-off-by: Larisa Grigore Co-developed-by: Ciprian Marian Costea Signed-off-by: Ciprian Marian Costea Reviewed-by: Frank Li --- drivers/dma/fsl-edma-common.h | 3 + drivers/dma/fsl-edma-main.c | 109 +++++++++++++++++++++++++++++++++- 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index ce37e1ee9c46..707fea4139b6 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -68,6 +68,8 @@ #define EDMA_V3_CH_CSR_EEI BIT(2) #define EDMA_V3_CH_CSR_DONE BIT(30) #define EDMA_V3_CH_CSR_ACTIVE BIT(31) +#define EDMA_V3_CH_ES_ERR BIT(31) +#define EDMA_V3_MP_ES_VLD BIT(31) enum fsl_edma_pm_state { RUNNING = 0, @@ -240,6 +242,7 @@ struct fsl_edma_engine { const struct fsl_edma_drvdata *drvdata; u32 n_chans; int txirq; + int txirq_16_31; int errirq; bool big_endian; struct edma_regs regs; diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 9873cce00c68..c9e3252d0da0 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -3,10 +3,11 @@ * drivers/dma/fsl-edma.c * * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2024 NXP * * Driver for the Freescale eDMA engine with flexible channel multiplexing * capability for DMA request sources. The eDMA block can be found on some - * Vybrid and Layerscape SoCs. + * Vybrid, Layerscape and S32G SoCs. */ #include @@ -72,6 +73,60 @@ static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id) return fsl_edma_tx_handler(irq, fsl_chan->edma); } +static irqreturn_t fsl_edma3_or_tx_handler(int irq, void *dev_id, + u8 start, u8 end) +{ + struct fsl_edma_engine *fsl_edma = dev_id; + struct fsl_edma_chan *chan; + int i; + + end = min(end, fsl_edma->n_chans); + + for (i = start; i < end; i++) { + chan = &fsl_edma->chans[i]; + + fsl_edma3_tx_handler(irq, chan); + } + + return IRQ_HANDLED; +} + +static irqreturn_t fsl_edma3_tx_0_15_handler(int irq, void *dev_id) +{ + return fsl_edma3_or_tx_handler(irq, dev_id, 0, 16); +} + +static irqreturn_t fsl_edma3_tx_16_31_handler(int irq, void *dev_id) +{ + return fsl_edma3_or_tx_handler(irq, dev_id, 16, 32); +} + +static irqreturn_t fsl_edma3_or_err_handler(int irq, void *dev_id) +{ + struct fsl_edma_engine *fsl_edma = dev_id; + struct edma_regs *regs = &fsl_edma->regs; + unsigned int err, ch, ch_es; + struct fsl_edma_chan *chan; + + err = edma_readl(fsl_edma, regs->es); + if (!(err & EDMA_V3_MP_ES_VLD)) + return IRQ_NONE; + + for (ch = 0; ch < fsl_edma->n_chans; ch++) { + chan = &fsl_edma->chans[ch]; + + ch_es = edma_readl_chreg(chan, ch_es); + if (!(ch_es & EDMA_V3_CH_ES_ERR)) + continue; + + edma_writel_chreg(chan, EDMA_V3_CH_ES_ERR, ch_es); + fsl_edma_disable_request(chan); + fsl_edma->chans[ch].status = DMA_ERROR; + } + + return IRQ_HANDLED; +} + static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) { struct fsl_edma_engine *fsl_edma = dev_id; @@ -274,6 +329,49 @@ static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engi return 0; } +static int fsl_edma3_or_irq_init(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma) +{ + int ret; + + fsl_edma->txirq = platform_get_irq_byname(pdev, "tx-0-15"); + if (fsl_edma->txirq < 0) + return fsl_edma->txirq; + + fsl_edma->txirq_16_31 = platform_get_irq_byname(pdev, "tx-16-31"); + if (fsl_edma->txirq_16_31 < 0) + return fsl_edma->txirq_16_31; + + fsl_edma->errirq = platform_get_irq_byname(pdev, "err"); + if (fsl_edma->errirq < 0) + return fsl_edma->errirq; + + ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, + fsl_edma3_tx_0_15_handler, 0, "eDMA tx0_15", + fsl_edma); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Can't register eDMA tx0_15 IRQ.\n"); + + if (fsl_edma->n_chans > 16) { + ret = devm_request_irq(&pdev->dev, fsl_edma->txirq_16_31, + fsl_edma3_tx_16_31_handler, 0, + "eDMA tx16_31", fsl_edma); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Can't register eDMA tx16_31 IRQ.\n"); + } + + ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, + fsl_edma3_or_err_handler, 0, "eDMA err", + fsl_edma); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Can't register eDMA err IRQ.\n"); + + return 0; +} + static int fsl_edma2_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) @@ -404,6 +502,14 @@ static struct fsl_edma_drvdata imx95_data5 = { .setup_irq = fsl_edma3_irq_init, }; +static const struct fsl_edma_drvdata s32g2_data = { + .dmamuxs = DMAMUX_NR, + .chreg_space_sz = EDMA_TCD, + .chreg_off = 0x4000, + .flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MUX_SWAP, + .setup_irq = fsl_edma3_or_irq_init, +}; + static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, @@ -413,6 +519,7 @@ static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, + { .compatible = "nxp,s32g2-edma", .data = &s32g2_data}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);