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Thu, 16 Jan 2025 07:44:57 -0800 From: Mohan Kumar D To: , , CC: , , , , Mohan Kumar D Subject: [PATCH 2/2] dmaengine: tegra210-adma: check for adma max page Date: Thu, 16 Jan 2025 21:14:39 +0530 Message-ID: <20250116154439.3889536-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116154439.3889536-1-mkumard@nvidia.com> References: <20250116154439.3889536-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|PH7PR12MB6980:EE_ X-MS-Office365-Filtering-Correlation-Id: 59aea5b3-1f61-4c4b-2424-08dd3644c0d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: KbnpLfLfbqOGiBAhr/13vBKhk73rQBY6H6xMhaXIZ0bGBMB37/OQgoQUWMwAUzUcCu5b8gjqvIjifFGuek43Rd3LtS5gyEv+pjOoYUT1sF7hWPXKQCfXMQAoU5FUWyyfW4ROCATFoM30alwh12oXlpl7f5O4droUl/PcTRmF5q5vQFJ7ecbdP0z9nBjPtRjTos2yOjcrO5WtukEXL69I+Ucl5mifpvud6nEEtp7Qvv2V/jhwLXLL1Jr6Fb55pVqE6Qm+/v3YSHe/TFk1HW27e2nJozYkzDvebWqGaPvozBD/BCElkfPNIDyFhMnV1FcIWpOfsMNeoct+9sc1LkwEYpVBKL00hbw/L7XDpuCGJEt8BnJiQoCrzZ8JTf4053nKL1PeiCpuGmNNKTr8jK/TDqN+ylzjgAz4KggLlrz3V0VAAIICv46T6sIN94ZeJE6acXDN1QBas57k4k3yv58pJZg3QsQnViE5L6RI97GhxEk8NKPlWyAhFUjo8LWlNDJ/cXhxxsL0BwOJ0ouB5BP5/Nm2UQowbabPnCBpWI2mclnGcj5vjhmlhOZBCXq7PfdKu9co/t5/mSePlCCnDksoABy3HXonPaX0LzGf/l1Wc4uqR54SMgzhKr03XI/ukCwKWIp1KtaMt0lrnEZcwV+sPOADzYvTBarFdy+1r7UNT2NSMk8RoGWRmviYBJNTUrKnR8AK9mHdHaVMUDIFUXx+nQQzZ9069R8SxQFqox+QeGlh8Q8t+f7BoCKSYI7x9PfgDSqSaTv3ztRB9PRqt1FUPV51lD3Vh/b7j99FwSCM84bf8Q/r1BWnvMmKCdrsKLiO2TLUbjtpJcWUyi5Wo4dK0s5fyfRjDMTL/gm5W1YHvyctHcL3Cqn7FPzMRzQ75fwy2zzV948kox1OlcNfkFO2+daWv11VlZTZ7MLGSiXQbdim50O2A1r+6qLYDevP/9Oo8LF4dv1/v3FoDFnqkGWbt13zFG1r9YAVws0TjfYFhH3Dvh5TUyGDc1jZM4Wd8xETo5NnYvGCp+dm6waz8qHbbVWpA5BiwE+C4KSMkXigMOZeRYAww/Ert2Qs0l311q07Wx4D0tklR9Zs5dwmuQfRa7svxtBq/jK7a+E6KtH1jFq41ZlfESIZFtjWr7HVF2caWd4dIlL61vqap0zK1RYcB4aCHQb/H1p+eS3LbxHGrmoq0iMKGT7NN9dpITQsqzmrT2/DAxx4/8TkjNg+ympwMhH261F4WZ/DpF57iQN8hbVP3BhW2jFRiJaDjS6xTcADlYWNmwj65Z35jVsvj4RjbvjzzMIPrVihmHf3POMsmLM8foabvW9uHrJ+DkfQbLAYuobF9+9rLKxaEJiCNLqQvGY1WsYcw/+jPqO+963wZ18oNrnZvfSsb2xpy5zMFfnJ4iZQCLdwQm7i61VlH6C6F8EA9A+ZG9j9Dxp4o1eVV1xcn50gHZF5X9nfnDTj89AVBKGecBEEvUutWHsDDmT86VQlBcLsqRzqTdPDD+ZGTZU= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 15:45:07.5851 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59aea5b3-1f61-4c4b-2424-08dd3644c0d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6980 Have additional check for max channel page during the probe to cover if any offset overshoot happens due to wrong DT configuration. Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 258220c9cb50..393e8a8a5bc1 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -83,7 +83,9 @@ struct tegra_adma; * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. * @sreq_index_offset: Slave channel index offset. + * @max_page: Maximum ADMA Channel Page. * @has_outstanding_reqs: If DMA channel can have outstanding requests. + * @set_global_pg_config: Global page programming. */ struct tegra_adma_chip_data { unsigned int (*adma_get_burst_config)(unsigned int burst_size); @@ -99,6 +101,7 @@ struct tegra_adma_chip_data { unsigned int nr_channels; unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; + unsigned int max_page; bool has_outstanding_reqs; void (*set_global_pg_config)(struct tegra_adma *tdma); }; @@ -854,6 +857,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .nr_channels = 22, .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, + .max_page = 0, .has_outstanding_reqs = false, .set_global_pg_config = NULL, }; @@ -871,6 +875,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .nr_channels = 32, .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, + .max_page = 4, .has_outstanding_reqs = true, .set_global_pg_config = tegra186_adma_global_page_config, }; @@ -922,7 +927,7 @@ static int tegra_adma_probe(struct platform_device *pdev) page_offset = lower_32_bits(res_page->start) - lower_32_bits(res_base->start); page_no = page_offset / cdata->ch_base_offset; - if (page_no == 0) + if (page_no == 0 || page_no > cdata->max_page) return -EINVAL; tdma->ch_page_no = page_no - 1;