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Thu, 16 Jan 2025 08:20:41 -0800 From: Mohan Kumar D To: , , CC: , , , , Mohan Kumar D Subject: [PATCH v3 2/2] dmaengine: tegra210-adma: check for adma max page Date: Thu, 16 Jan 2025 21:50:33 +0530 Message-ID: <20250116162033.3922252-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116162033.3922252-1-mkumard@nvidia.com> References: <20250116162033.3922252-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|CYYPR12MB8923:EE_ X-MS-Office365-Filtering-Correlation-Id: 307e1fad-3191-4f8b-c073-08dd3649c80b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: J80yIp6KPr7Dj2et/LmloK5+moWGbFxFVUIukc18CaBMYla3Ts7apcIuf0wXbMue4PuavUgUp+y58PdWTZ9cP6Bl+6YuRFKC+I7+6SctGNQLd+Pi6Kg1QB8oI1mpd/UInpiAyR7/8Q7bmbvikd8ibmWK3tUbZIebmhtXl8hFkax8AsKT+ApS0viwdDp3mJLqX80bEgx3RsQqOXeGR/M5tvMh6WweAwtrNH1s4I5AlpFuSmq2DMqsvIepRwx8s7820QiJOeJa3ng5wQF0hNP6DEb3k85rI2y8rp1YL5OOi7TPFGructi47H2TbzfuCoSAKQrduQps0NH6bOABQCK6Uh5B56Mk+63gVcAoU2sKLwSqwHvQ+LZSZbXzwTuXQYS/y06nrFO+XQFku5JIgOh6dn1uKzFfymt3rLMO4XghZ+WVuEZJZ8ZN2/7160IwYii1mNC+mFnb1ZwWVNp50Qa0LcQXDy8C2/DS2QvoTbtwBzyOLgwpMepierqx0hVw+fiwGC8XMU8AUoA8GwAftC6AkAxw9t/1qFY3LXgXvZHUmSIE9sskvImE9enAyi3xkg/rJ3Z29zpxgVkIw4kLCvCzTX/4QVJeOGm4ZBYn4KgCwxiEiVsu9r5MvxcU9tSTX+S4wOA9fg+35dwhN3lr4aLf6XMCj5+FW+BuiVsUZ+d0N5iLMSRQN7fmNOubexDGvanHl0k9lxxX5WogxUM6gtVblU9CobpzK48HopPwU+Xmc/VChTfIXF1jhd2APDsL6hXE+EiXHJcIEeFq93AXnRISbnsNZkbpK971oJiS1x2Jt6Yrt3DvH/LaEiTa7O7nfZWHs5hj+Ckj7IwDno3qoqkRCho0uEsxuyMdE645oZaEaSUqoiSowwW1wJH1V0BPnq0/WEYZWe0FVXmQ99kaI4xn6DgxlAxzE0I4cnvOGcEupui0SaQdCQN0BT88f6Hc8OJLTyB/N19ivR+H7i82r5l312JoMlVlEmkiMJrXmQ5SW/BWTdGGqtufdt5RvlISCJH3I09iX68IfsnWKntaAFqNMKTeRgX4czoHdEDv5ItaPMgYCN78mZKpFm9G+WkczK04AIL5IbOZiEkQDXlmXGX3nJMk4k5Sihlo4RTWHwCx0DFzBsUhyjn5x/3CPWdP3pW3HULGQUTGfklh1ttyAYBdkZgTNvA3OXMmY5n6Ln1n+gKz22faqhn6ZSHueyuaE+Ts4ZCfcXOyiVtWiBrrpLH/YxgynVnvrxzj1ey365poTgyoprxkWG+zUc0usYEp0T2BSrfsipCJx/83s9Os7hCEQTBWtUDBvq0TFVZJo6Q6xTjsGZ3vCM2rkCHj+/OXpmrO+tGUOLya0Raei1XSx0lMbwIZPK9OZBn12KOK0+wLr5yGbqS0LsKIquSJvxfqU3wMybvWkqqvUiaaLERbV+zmmVpZ4FQnAxUgSWQKvJohUFsWIVWFW1Ow4zK0+fyn71vi5DEOEa47NG9hWJr5Lei1WdNI5oRtOyKmPGaf8J2hyvY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 16:21:07.1173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 307e1fad-3191-4f8b-c073-08dd3649c80b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8923 Have additional check for max channel page during the probe to cover if any offset overshoot happens due to wrong DT configuration. Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Cc: stable@vger.kernel.org Signed-off-by: Mohan Kumar D Reviewed-by: Jon Hunter --- drivers/dma/tegra210-adma.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 258220c9cb50..393e8a8a5bc1 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -83,7 +83,9 @@ struct tegra_adma; * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. * @sreq_index_offset: Slave channel index offset. + * @max_page: Maximum ADMA Channel Page. * @has_outstanding_reqs: If DMA channel can have outstanding requests. + * @set_global_pg_config: Global page programming. */ struct tegra_adma_chip_data { unsigned int (*adma_get_burst_config)(unsigned int burst_size); @@ -99,6 +101,7 @@ struct tegra_adma_chip_data { unsigned int nr_channels; unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; + unsigned int max_page; bool has_outstanding_reqs; void (*set_global_pg_config)(struct tegra_adma *tdma); }; @@ -854,6 +857,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .nr_channels = 22, .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, + .max_page = 0, .has_outstanding_reqs = false, .set_global_pg_config = NULL, }; @@ -871,6 +875,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .nr_channels = 32, .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, + .max_page = 4, .has_outstanding_reqs = true, .set_global_pg_config = tegra186_adma_global_page_config, }; @@ -922,7 +927,7 @@ static int tegra_adma_probe(struct platform_device *pdev) page_offset = lower_32_bits(res_page->start) - lower_32_bits(res_base->start); page_no = page_offset / cdata->ch_base_offset; - if (page_no == 0) + if (page_no == 0 || page_no > cdata->max_page) return -EINVAL; tdma->ch_page_no = page_no - 1;