| Message ID | 3dc5d31428846326bf122a2a9b402a2a80e97681.1406766014.git.horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Vinod Koul |
| Headers | show |
On Thu, Jul 31, 2014 at 2:34 AM, Simon Horman <horms+renesas@verge.net.au> wrote: > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt > @@ -0,0 +1,98 @@ > +* Renesas R-Car DMA Controller Device Tree bindings > + > +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA > +controller instances named DMAC capable of serving multiple clients. Channels > +can be dedicated to specific clients or shared between a large number of > +clients. > + > +DMA clients are connected to the DMAC ports referenced by an 8-bit identifier > +called MID/RID. I think the above sentence can be removed, as it's superseded by the first sentence of the successive paragraph: > + > +Each DMA client is connected to one dedicated port of the DMAC, identified by > +an 8-bit port number called the MID/RID. A DMA controller can thus serve up to > +256 clients in total. When the number of hardware channels is lower than the > +number of clients to be served, channels must be shared between multiple DMA > +clients. The association of DMA clients to DMAC channels is fully dynamic and > +not described in these device tree bindings. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Geert, Thank you for the review. On Monday 04 August 2014 10:05:49 Geert Uytterhoeven wrote: > On Thu, Jul 31, 2014 at 2:34 AM, Simon Horman wrote: > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt > > @@ -0,0 +1,98 @@ > > +* Renesas R-Car DMA Controller Device Tree bindings > > + > > +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA > > +controller instances named DMAC capable of serving multiple clients. > > Channels +can be dedicated to specific clients or shared between a large > > number of +clients. > > + > > +DMA clients are connected to the DMAC ports referenced by an 8-bit > > identifier +called MID/RID. > > I think the above sentence can be removed, as it's superseded by the first > sentence of the successive paragraph: I've probably just forgotten to remove the sentence while reworking the documentation. Thanks for reporting it, I'll fix that in the next version. > > + > > +Each DMA client is connected to one dedicated port of the DMAC, > > identified by +an 8-bit port number called the MID/RID. A DMA controller > > can thus serve up to +256 clients in total. When the number of hardware > > channels is lower than the +number of clients to be served, channels must > > be shared between multiple DMA +clients. The association of DMA clients > > to DMAC channels is fully dynamic and +not described in these device tree > > bindings.
On Mon, Aug 04, 2014 at 04:01:42PM +0200, Laurent Pinchart wrote: > Hi Geert, > > Thank you for the review. > > On Monday 04 August 2014 10:05:49 Geert Uytterhoeven wrote: > > On Thu, Jul 31, 2014 at 2:34 AM, Simon Horman wrote: > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt > > > @@ -0,0 +1,98 @@ > > > +* Renesas R-Car DMA Controller Device Tree bindings > > > + > > > +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA > > > +controller instances named DMAC capable of serving multiple clients. > > > Channels +can be dedicated to specific clients or shared between a large > > > number of +clients. > > > + > > > +DMA clients are connected to the DMAC ports referenced by an 8-bit > > > identifier +called MID/RID. > > > > I think the above sentence can be removed, as it's superseded by the first > > sentence of the successive paragraph: > > I've probably just forgotten to remove the sentence while reworking the > documentation. Thanks for reporting it, I'll fix that in the next version. BTW, I believe Vinod has already applied this and the previous three patches of this series to his tree. As he applied then rather than pulling the pull-request I sent I intend to drop the entire series from my tree for now. > > > + > > > +Each DMA client is connected to one dedicated port of the DMAC, > > > identified by +an 8-bit port number called the MID/RID. A DMA controller > > > can thus serve up to +256 clients in total. When the number of hardware > > > channels is lower than the +number of clients to be served, channels must > > > be shared between multiple DMA +clients. The association of DMA clients > > > to DMAC channels is fully dynamic and +not described in these device tree > > > bindings. > > -- > Regards, > > Laurent Pinchart > > -- > To unsubscribe from this list: send the line "unsubscribe linux-sh" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Simon, On Tuesday 05 August 2014 10:46:42 Simon Horman wrote: > On Mon, Aug 04, 2014 at 04:01:42PM +0200, Laurent Pinchart wrote: > > On Monday 04 August 2014 10:05:49 Geert Uytterhoeven wrote: > >> On Thu, Jul 31, 2014 at 2:34 AM, Simon Horman wrote: > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt > >>> @@ -0,0 +1,98 @@ > >>> +* Renesas R-Car DMA Controller Device Tree bindings > >>> + > >>> +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA > >>> +controller instances named DMAC capable of serving multiple clients. > >>> Channels > >>> +can be dedicated to specific clients or shared between a large number > >>> of > >>> +clients. > >>> + > >>> +DMA clients are connected to the DMAC ports referenced by an 8-bit > >>> identifier +called MID/RID. > >> > >> I think the above sentence can be removed, as it's superseded by the > >> first sentence of the successive paragraph: > >> > > I've probably just forgotten to remove the sentence while reworking the > > documentation. Thanks for reporting it, I'll fix that in the next version. > > BTW, I believe Vinod has already applied this and the previous three > patches of this series to his tree. Indeed. I'm surprised to see the DT bindings being merged without the driver, but given that they seem to be OK, that's not a problem. > As he applied then rather than pulling the pull-request I sent I intend > to drop the entire series from my tree for now. Please do. I'll resubmit the remaining patches.
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt new file mode 100644 index 0000000..df0f48b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -0,0 +1,98 @@ +* Renesas R-Car DMA Controller Device Tree bindings + +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA +controller instances named DMAC capable of serving multiple clients. Channels +can be dedicated to specific clients or shared between a large number of +clients. + +DMA clients are connected to the DMAC ports referenced by an 8-bit identifier +called MID/RID. + +Each DMA client is connected to one dedicated port of the DMAC, identified by +an 8-bit port number called the MID/RID. A DMA controller can thus serve up to +256 clients in total. When the number of hardware channels is lower than the +number of clients to be served, channels must be shared between multiple DMA +clients. The association of DMA clients to DMAC channels is fully dynamic and +not described in these device tree bindings. + +Required Properties: + +- compatible: must contain "renesas,rcar-dmac" + +- reg: base address and length of the registers block for the DMAC + +- interrupts: interrupt specifiers for the DMAC, one for each entry in + interrupt-names. +- interrupt-names: one entry per channel, named "ch%u", where %u is the + channel number ranging from zero to the number of channels minus one. + +- clock-names: "fck" for the functional clock +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: must contain "fck" for the functional clock. + +- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port + connected to the DMA client +- dma-channels: number of DMA channels + +Example: R8A7790 (R-Car H2) SYS-DMACs + + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + };