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Thu, 23 Jul 2015 03:39:09 +0000 Received: from b50113.ap.freescale.net (b50113.ap.freescale.net [10.192.241.89]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6N3d5Rr027964; Wed, 22 Jul 2015 20:39:07 -0700 From: Zidan Wang To: CC: , , Zidan Wang Subject: [PATCH] dma: imx-sdma: Add imx6sx platform support Date: Thu, 23 Jul 2015 11:40:49 +0800 Message-ID: <5fe1c8de485dc1c8cb518f5a8b89b66be21e661a.1437622767.git.zidan.wang@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD039; 1:PlCmAfzlhFC2P+w4n1bMRiPWDl+boWqCyHg08gac19I6uxRgqDVPQ1R9q1RUH3KHDd6FS9yvDyF+umSOdZKbg0Aslk4Xctg3CqN/tkXdVSATmSc+gwJK/Qc+kHKV8flvuZe+9pUNWSV2jqdWPv0DuoHf083K8jz7p41DhC6RsIBU/oxCCAceZ9mriIWJsp/sfdSjfDp6MWLYC3fDgbNlN/KEw2Q9SK2PlUhHGVapD/2rZuGugTFkqGDvsHGodRj/6UH31TlSXfXr3n+NWeQJr6d9TtUkqwBDa/wJp0sqWNU+Egw+aMrba1pp1UfjFDCtl1A2kAcMEp6wc+z59DKAWnOPTZvH41AeIktPlCMERpoV2OGQ5cHUGq7tiYtNgPBFB40onke0yiFpjQArLFrJJaOpHmEzLIhTtOOHN51HbacbqRoqik4SQR8waaAAR1Lm X-Forefront-Antispam-Report: CIP:192.88.168.50; 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DM2PR0301MB1262; 5:JCGz32+6slHq2WKBRVUVYNyBxrUb114T4aVM2mR7++4/H6wXNenmQEEw2QTthz8zlkwC11H5JERLWNUnj19rs40iDrdgb5qPAbADZD3W7WpqyjnCANg36YlIAlmEc0TK8nb3jtsyGqh4IKFKHVPJMw==; 24:cbHXcKafOP6UMG4r5dv/+D1V31uElzhPIbG8ZXiT2qQjaFCxSJW9HZ4xeTcOVrLe+YLkCvSj6SdWjJCzWuKymNWzcfLEs1+JBHXtNV8OxZ0=; 20:bPFhUzwPdSLh2B1r+uFuke+ywVgfwM/1M96HBpZgArp6u6zmVLuT6UZ9Qu/1gGg01eUaQLYvkAGl45i5a9MVRw== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2015 03:39:09.1256 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB1262 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new Solo X has more requirements for SDMA events. So it creates a event mux to remap most of event numbers in GPR (General Purpose Register). If we want to use SDMA support for those module who do not get the even number as default, we need to configure GPR first. Thus this patch adds this support of GPR event remapping configuration to the SDMA driver. Signed-off-by: Zidan Wang --- drivers/dma/imx-sdma.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 77b6aab..6efb116 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -41,6 +41,9 @@ #include #include #include +#include +#include +#include #include "dmaengine.h" @@ -1337,6 +1340,72 @@ err_firmware: release_firmware(fw); } +#define EVENT_REMAP_CELLS 3 + +static int __init sdma_event_remap(struct sdma_engine *sdma) +{ + struct device_node *np = sdma->dev->of_node; + struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); + struct property *event_remap; + struct regmap *gpr; + char propname[] = "fsl,sdma-event-remap"; + u32 reg, val, shift, num_map, i; + int ret = 0; + + if (IS_ERR(np) || IS_ERR(gpr_np)) + goto out; + + event_remap = of_find_property(np, propname, NULL); + num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; + if (!num_map) { + dev_warn(sdma->dev, "no event needs to be remapped\n"); + goto out; + } else if (num_map % EVENT_REMAP_CELLS) { + dev_err(sdma->dev, "the property %s must modulo %d\n", + propname, EVENT_REMAP_CELLS); + ret = -EINVAL; + goto out; + } + + gpr = syscon_node_to_regmap(gpr_np); + if (IS_ERR(gpr)) { + dev_err(sdma->dev, "failed to get gpr regmap\n"); + ret = PTR_ERR(gpr); + goto out; + } + + for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { + ret = of_property_read_u32_index(np, propname, i, ®); + if (ret) { + dev_err(sdma->dev, "failed to read property %s index %d\n", + propname, i); + goto out; + } + + ret = of_property_read_u32_index(np, propname, i + 1, &shift); + if (ret) { + dev_err(sdma->dev, "failed to read property %s index %d\n", + propname, i + 1); + goto out; + } + + ret = of_property_read_u32_index(np, propname, i + 2, &val); + if (ret) { + dev_err(sdma->dev, "failed to read property %s index %d\n", + propname, i + 2); + goto out; + } + + regmap_update_bits(gpr, reg, BIT(shift), val << shift); + } + +out: + if (!IS_ERR(gpr_np)) + of_node_put(gpr_np); + + return ret; +} + static int sdma_get_firmware(struct sdma_engine *sdma, const char *fw_name) { @@ -1551,6 +1620,10 @@ static int sdma_probe(struct platform_device *pdev) if (ret) goto err_init; + ret = sdma_event_remap(sdma); + if (ret) + goto err_init; + if (sdma->drvdata->script_addrs) sdma_add_scripts(sdma, sdma->drvdata->script_addrs); if (pdata && pdata->script_addrs)