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Tue, 18 May 2021 13:24:03 +0000 Date: Tue, 18 May 2021 15:23:34 +0200 From: Olivier Dautricourt To: Rob Herring , Vinod Koul , Stefan Roese Cc: Olivier Dautricourt , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/3] dt-bindings: dma: add schema for altera-msgdma Message-ID: <7d77772f49b978e3d52d3815b8743fe54c816994.1621343877.git.olivier.dautricourt@orolia.com> Content-Disposition: inline X-Originating-IP: [2a01:e34:ec42:fd70:167:681b:bc47:e8b1] X-ClientProxiedBy: PAZP264CA0014.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:21::19) To PR1PR06MB4746.eurprd06.prod.outlook.com (2603:10a6:102:11::28) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from orolia.com (2a01:e34:ec42:fd70:167:681b:bc47:e8b1) by PAZP264CA0014.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; Tue, 18 May 2021 13:24:03 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f167caf5-e30c-405c-cb1f-08d91a0034ac X-MS-TrafficTypeDiagnostic: PR3PR06MB6715: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:304; 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Reviewed-by: Stefan Roese Signed-off-by: Olivier Dautricourt Reviewed-by: Rob Herring --- Notes: Changes in v2: - fix reg size in dt example - fix dt_binding check warning - add list in MAINTAINERS entry Changes from v2 to v3: none Changes from v3 to v4: none Changes from v4 to v5: as per Rob's comments: - change compatible field from 'altr,msgdma' to 'altr,socfpga-msgdma' to indicate that it's compatible with altera socfpga family. - describe each region separately - remove maxItems/minItems for reg section. as per Vinod's comments: - separate MAINTAINERS editing in another commit - remove description for #dma-cells .../devicetree/bindings/dma/altr,msgdma.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/altr,msgdma.yaml -- 2.31.0.rc2 diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml new file mode 100644 index 000000000000..ce51531e8736 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera mSGDMA IP core + +maintainers: + - Olivier Dautricourt + +description: | + Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) + intellectual property (IP) + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + const: altr,socfpga-msgdma + + reg: + items: + - description: Control and Status Register Slave Port + - description: Descriptor Slave Port + - description: Response Slave Port + + reg-names: + items: + - const: csr + - const: desc + - const: resp + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + msgdma_controller: dma-controller@ff200b00 { + compatible = "altr,socfpga-msgdma"; + reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>; + reg-names = "csr", "desc", "resp"; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + };