From patchwork Tue Jan 9 07:36:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara Rao X-Patchwork-Id: 10151031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 815F1602B3 for ; Tue, 9 Jan 2018 07:36:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 756A428787 for ; Tue, 9 Jan 2018 07:36:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68DD72878E; Tue, 9 Jan 2018 07:36:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C943528787 for ; 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Tue, 9 Jan 2018 07:36:11 +0000 Received: from CY1PR02MB1692.namprd02.prod.outlook.com ([10.162.161.26]) by CY1PR02MB1692.namprd02.prod.outlook.com ([10.162.161.26]) with mapi id 15.20.0386.008; Tue, 9 Jan 2018 07:36:11 +0000 From: Appana Durga Kedareswara Rao To: Vinod Koul CC: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Thread-Topic: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Thread-Index: AQHThF33WrKalX9l5EWNOde69xcPPqNp0PuA////B9CAAG1tgIAAAo7AgADBmQD///894IAABTEAgAAVQqA= Date: Tue, 9 Jan 2018 07:36:11 +0000 Message-ID: References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> <20180109044858.GN18649@localhost> <20180109050449.GO18649@localhost> In-Reply-To: <20180109050449.GO18649@localhost> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=appanad@xilinx.com; x-originating-ip: [182.72.145.30] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; CY1PR02MB1692; 7:JC4frkEtQQ+ooSrSyfOAslWp/t6nr6RyF/PXQkHJyaFPhNnxcfXG1mkVjbtNwTYEU2U0O2hBcee8W+cUJfXSc6nbIxt5edN6J09pgEjs++qr2lIq5LyqXHiSvoaJSJzuwKIA7y1l0W4jSq8fVceF2c2m2IfU8NrCokhwrXeuSfPgKcj8A9HqlCw4dQMaCQc/sGWfCHlcjUzj47SRXwmDrc8bAwoYWXTgiUpd0MWma5W1cOgSadC/jsTDFOt4n1oR x-ms-exchange-antispam-srfa-diagnostics: SSOS; x-ms-office365-filtering-correlation-id: d307a5ca-c449-470b-ff51-08d55733a7f5 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(5600026)(4604075)(3008032)(4534020)(4602075)(7168020)(4627115)(201703031133081)(201702281549075)(48565401081)(2017052603307)(7153060)(7193020); SRVR:CY1PR02MB1692; x-ms-traffictypediagnostic: CY1PR02MB1692: x-ld-processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040470)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231023)(944501075)(6055026)(6041268)(20161123560045)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(6072148)(201708071742011); SRVR:CY1PR02MB1692; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:CY1PR02MB1692; x-forefront-prvs: 0547116B72 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(39380400002)(39860400002)(376002)(366004)(396003)(51914003)(24454002)(189003)(199004)(7696005)(6116002)(59450400001)(76176011)(55016002)(99286004)(3846002)(53936002)(68736007)(478600001)(9686003)(14454004)(5660300001)(2950100002)(7416002)(74316002)(6916009)(93886005)(102836004)(7736002)(2900100001)(6436002)(6246003)(229853002)(55236004)(25786009)(3660700001)(6506007)(54906003)(3280700002)(106356001)(105586002)(4326008)(316002)(77096006)(39060400002)(81156014)(97736004)(81166006)(2906002)(8676002)(33656002)(305945005)(8936002)(66066001)(86362001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR02MB1692; H:CY1PR02MB1692.namprd02.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: xilinx.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: nGAwtke4/QOcPYSaUUoXupx1yiI1TqBunA6kccRSrni3FWSvGVuKCL4GFzgLrIetBr9lxF2rIl+30Xih7p1I0Q== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: d307a5ca-c449-470b-ff51-08d55733a7f5 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2018 07:36:11.4252 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1692 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, Thanks for the review... >On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao >wrote: >> Hi, >> >> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara >> >Rao >> >wrote: >> >> Hi, >> >> >> >> >> >> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); >> >> >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); >> >> >> > >> >> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? >> >> >> >What is value of addr_width here typically? Usually controllers >> >> >> >can support different widths and this is a surprise that you >> >> >> >support only one value >> >> >> >> >> >> Controller supports address width of 32 and 64. >> >> > >> >> >Then this should have both 32 and 64 values here >> >> >> >> Address width is configurable parameter at the h/w level. >> >> Since this IP is a soft IP user can create a design with either >> >> 32-bit or 64-bit address configuration. >> > >> >and not both right? >> >> Yes not both at the same time... >> Axi dma controller can be configured for either 32-bit or 64-bit address... > >So my suspicion was correct. I would suggest you to read up on the >documentation again. The src/dst_addr_widths has _nothing_ to do with 32/64 >bit addresses used. > >It is the capability of the dma controller to do transfers with data width as 8bits, >16 bits, so on. iKey is "data width" and not address type. >This typically translates to DMA FIFO configuration of the controller! Thanks for the detailed explanation... I have gone through the spec again controller does supports 1 byte, 2 byte, 4 byte up to 128 byte transfers. In order to do variable length transfers user needs to drive a valid value to the tkeep strobe signal at the h/w level. And user needs to configure the below parameters c_m_axis_mm2s_tdata_width or c_m_axis_s2mm_tdata_width With desired configuration at the h/w level. Controller supports data width of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits (i.e. c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width parameters range) At the s/w level currently we are getting c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width Configuration as xlnx,datawidth property in the device-tree. So proper values for the src/dst_addr width fields should be, datawidth property in bytes. Please correct me if I am wrong... Changes looks like below... Here width is in bytes based on the h/w configuration... Regards, Kedar. > >-- >~Vinod --- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -2411,6 +2411,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->direction = DMA_MEM_TO_DEV; chan->id = chan_id; chan->tdest = chan_id; + xdev->common.directions = BIT(DMA_MEM_TO_DEV); + xdev->common.src_addr_widths = BIT(width); chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -2428,6 +2430,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->direction = DMA_DEV_TO_MEM; chan->id = chan_id; chan->tdest = chan_id - xdev->nr_channels; + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); + xdev->common.dst_addr_widths = BIT(width); chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {