diff mbox series

[2/2] damengine: dw-edma: Add msi wartermark configuration

Message ID SYBP282MB2620CCF5690B0CDC437E3205F9D72@SYBP282MB2620.AUSP282.PROD.OUTLOOK.COM (mailing list archive)
State Changes Requested
Headers show
Series [1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() | expand

Commit Message

zheng.dongxiong June 27, 2024, 12:09 p.m. UTC 
HDMA trigger wartermark interrupt, When use the RIE flag.
PCIe RC will trigger AER, If msi wartermark addr is not configuration.
This patch fix it by add msi wartermark configuration

Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com>
---
 drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
index d77051d1e..c4d15a7a7 100644
--- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
@@ -280,6 +280,9 @@  static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)
 	/* MSI done addr - low, high */
 	SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo);
 	SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi);
+	/* MSI watermark addr - low, high */
+	SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb, chan->msi.address_lo);
+	SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb, chan->msi.address_hi);
 	/* MSI abort addr - low, high */
 	SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo);
 	SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi);