From patchwork Thu Sep 28 01:49:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Br=C3=BCns?= X-Patchwork-Id: 9975127 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CC6B760375 for ; Thu, 28 Sep 2017 01:50:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4414293C5 for ; Thu, 28 Sep 2017 01:50:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B8B39293C8; Thu, 28 Sep 2017 01:50:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 701E1293C5 for ; Thu, 28 Sep 2017 01:50:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752670AbdI1Bt5 (ORCPT ); Wed, 27 Sep 2017 21:49:57 -0400 Received: from mail-out-2.itc.rwth-aachen.de ([134.130.5.47]:64096 "EHLO mail-out-2.itc.rwth-aachen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752643AbdI1Bty (ORCPT ); Wed, 27 Sep 2017 21:49:54 -0400 X-IronPort-AV: E=Sophos;i="5.42,447,1500933600"; d="scan'208";a="15566064" Received: from rwthex-w2-a.rwth-ad.de ([134.130.26.158]) by mail-in-2.itc.rwth-aachen.de with ESMTP; 28 Sep 2017 03:49:53 +0200 Received: from pebbles.fritz.box (77.182.56.60) by rwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Thu, 28 Sep 2017 03:49:47 +0200 From: =?UTF-8?q?Stefan=20Br=C3=BCns?= To: CC: , Chen-Yu Tsai , Andre Przywara , , Dan Williams , Vinod Koul , Rob Herring , , Code Kipper , Maxime Ripard , , =?UTF-8?q?Stefan=20Br=C3=BCns?= Subject: [PATCH v4 08/11] dmaengine: sun6i: Add support for Allwinner A64 and compatibles Date: Thu, 28 Sep 2017 03:49:25 +0200 X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170928014928.2272-1-stefan.bruens@rwth-aachen.de> References: <20170928014928.2272-1-stefan.bruens@rwth-aachen.de> MIME-Version: 1.0 X-Originating-IP: [77.182.56.60] X-ClientProxiedBy: rwthex-w3-b.rwth-ad.de (2002:8682:1aa3::8682:1aa3) To rwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e) Message-ID: Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The A64 SoC has the same dma engine as the H3 (sun8i), with a reduced amount of physical channels. To allow future reuse of the compatible, leave the channel count etc. in the config data blank and retrieve it from the devicetree. Signed-off-by: Stefan Brüns Acked-by: Maxime Ripard --- Changes in v4: - Fix config initialization Changes in v3: - Omit default values from sun50i_a64_dma_cfg definition Changes in v2: None drivers/dma/sun6i-dma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index b5906da2a975..945436e477d7 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -1125,6 +1125,25 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), }; +/* + * The A64 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1152,6 +1171,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, + { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match);