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Mon, 7 Sep 2020 05:48:24 +0000 From: Yash Shah To: robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com Cc: aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v2 0/3] SiFive DDR controller and EDAC support Date: Mon, 7 Sep 2020 11:17:56 +0530 Message-Id: <1599457679-8947-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BM1PR01CA0141.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:40::35) To BN6PR1301MB2020.namprd13.prod.outlook.com (2603:10b6:405:34::34) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by BM1PR01CA0141.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:40::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3348.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: QqKYom2F9Tlf2ghh7lcRK/VsbTDnZwAywqfIUYLVohQu/AWbrsEmw98VFsNeuGe4+qErMY3/D0HDtUUpPfoAE6cch+Ykow9s/6ECWjWVPfyCpn8JhcDoxZeQMCOk58D4YP0EXW2tGvtdeTvRRVE0LZQf8eZkqOMKAqaN88D30zs4R2WYz4+kkEnXKc8CnthmJvDP+ni8Vqt7f38dTNClysm6cfK5KMMdIvuQXKPHbIBraF2yFm69r/AKxBkMl85Xt7vxHg0QASm4qi13mfv7HUZv6V2cR2+BEhYYD1KmMONWdg1shbVcHaMr/N8G0kVl6IL5PWC8+ySHFyO3CQUjmdAMUZ4u240baI44TY4Fsd0EeWVeL6qixWxxBXZtTDa6Fe728VZ8vHYQbCCCp7xrIw2Ucl/Xbr2xZpENRsHsQZBUaebsA+vEJqnm5z76Yx4gR7Sjz27VKPVUupd/FS8W+lEy8nCY565CFVOx2I77XgBoo2I4IFhzbhn9qCjzVtOaNMgK7xKopIOVr9kvnYgvwY5eObRKF1DDrVSymSG2FbUVybvBmddjcwykL2xZVRM+oPztXNiilNnd3taveBdH87QaXkxfb2R2alJb1UJeTJzfo3aaxyUKDyds/PjXME30qEroLnI4MKKngLCzEOq0NQ== X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: a93c577d-70ff-4c69-1a6a-08d852f1a289 X-MS-Exchange-CrossTenant-AuthSource: BN6PR1301MB2020.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2020 05:48:24.2634 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PeSSBTUR6HQlAyQ07UAmEHWbhsmS5iLKLXM3ZtqZQNxzvWFR9uM9CqjYbeqd79XV74KcElykbkyW0X3ucy6KYA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR13MB1569 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The series add supports for SiFive DDR controller driver. This driver is use to manage the Cadence DDR controller present in SiFive SoCs. Currently it manages only the EDAC feature of the DDR controller. The series also adds Memory controller EDAC support for SiFive platform. It register for notifier event from SiFive DDR controller driver. The series is tested and based on Linux v5.8. For testing on Hifive Unleashed: 1. Enable the ECC bit of DDR controller during DDR initialization 2. Erase the entire DRAM in bootloader stage 3. Using FWC feature of DDR controller force ecc error to test Changes in v2: Incorporate below changes in EDAC patch as suggested by Borislav Petkov - Replace all ifdeffery with if(IS_ENABLED(CONFIG_...)) - A few textual changes in patch description and code Yash Shah (3): dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs soc: sifive: Add SiFive specific Cadence DDR controller driver EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++ drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 119 +++++++++++- drivers/soc/sifive/Kconfig | 6 + drivers/soc/sifive/Makefile | 3 +- drivers/soc/sifive/sifive_ddr.c | 207 +++++++++++++++++++++ include/soc/sifive/sifive_ddr.h | 73 ++++++++ 7 files changed, 447 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml create mode 100644 drivers/soc/sifive/sifive_ddr.c create mode 100644 include/soc/sifive/sifive_ddr.h