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[v3,0/6] x86/mce: Handle error injection failures in mce-inject module

Message ID 20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com (mailing list archive)
Headers show
Series x86/mce: Handle error injection failures in mce-inject module | expand

Message

Smita Koralahalli Nov. 4, 2021, 9:58 p.m. UTC
This series of patches handles the scenarios where error injection
fails silently on mce-inject module. It also sets the valid bit in
MCA_STATUS register unconditionally to correct Val=0 injection made by the
user and finally returns error code to userspace on failures injecting the
module.

Error injection fails if the bank is unpopulated (MCA_IPID register reads
zero) or if the platform enforces write ignored behavior on status
registers.

The first patch checks for an unpopulated bank by reading the value out
from MCA_IPID register and the third patch checks for writes ignored from
MCA_STATUS and MCA_DESTAT.

The second patch sets valid bit before doing error injection.

The fourth and fifth patch does some cleanup in prepare_msrs(). No
functional changes in these two patches.

The final patch returns error code to userspace from mce-inject module.

Smita Koralahalli (6):
  x86/mce/inject: Check if a bank is unpopulated before error injection
  x86/mce/inject: Set the valid bit in MCA_STATUS before error injection
  x86/mce/inject: Check for writes ignored in status registers
  x86/mce/inject: Simplify evaluation of writes ignored in status
    registers
  x86/mce/inject: Restructure prepare_msrs()
  x86/mce/mce-inject: Return error code to userspace from mce-inject
    module

 arch/x86/kernel/cpu/mce/inject.c | 106 ++++++++++++++++++++++++++-----
 1 file changed, 90 insertions(+), 16 deletions(-)