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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT031.mail.protection.outlook.com (10.13.174.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:31 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:29 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 00/24] AMD MCA Address Translation Updates Date: Thu, 27 Jan 2022 20:40:51 +0000 Message-ID: <20220127204115.384161-1-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38d895fb-6ee6-41a6-8042-08d9e1d56681 X-MS-TrafficTypeDiagnostic: DM6PR12MB3802:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:31.1963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38d895fb-6ee6-41a6-8042-08d9e1d56681 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3802 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This patchset refactors the AMD MCA Address Translation code and adds support for newer systems. The reference code was recently refactored in preparation for updates for future systems. These patches try to follow the reference code as closely as possible. I also tried to address comments from previous patchset reviews. Patches 1-23 do the refactor without adding new system support. The goal is to break down the translation algorithm into smaller chunks. Code that changes between Data Fabric versions or interleaving modes is moved to a set of function pointers. The intention is that new system support can be added without any major refactor. I tried to make a patch for each logical change. The top level function was split first, then the next level of functions, etc. in a somewhat breadth-first approach. Patch 24 adds support for systems with Data Fabric version 3 (Rome and later). Each patch was build tested individually. The entire set was functionally tested with the following modes. Naples: No interleaving Channel interleaving Die interleaving Socket interleaving Rome: No interleaving Nodes-per-Socket 0 (NPS0) Nodes-per-Socket 1 (NPS1) Nodes-per-Socket 2 (NPS2) Nodes-per-Socket 4 (NPS4) NPS2 w/o hashing NPS4 w/o hashing Note to the maintainers: If there are no major issues, I'd like for this set to be applied, please. Comments are still welcome, of course. There will be a future set to add support for Family 19h Models 10h, etc., and I'd like to address comments there. Thanks, Yazen Link: https://lore.kernel.org/r/20211028175728.121452-1-yazen.ghannam@amd.com v3->v4: * Rebased on latest ras/edac-for-next. * Dropped patches merged in v5.17 (Thanks Boris!) * Dropped patches for CPU+GPU systems. * Dropped patch that changed function parameters. * Folded glossary patch into other patches. * Left in pr_debug() statements that I found useful during development. v2->v3: * Drop "df_regs" use. * Include patches needed for CPU+GPU systems. * Set "df_ops" at module init based on family type. v1->v2: * Move address translation code to EDAC. * Use function pointers to handle code differences between DF versions. * Add glossary of acronyms. Yazen Ghannam (24): EDAC/amd64: Define Data Fabric operations EDAC/amd64: Define functions for DramOffset EDAC/amd64: Define function to read DRAM address map registers EDAC/amd64: Define function to find interleaving mode EDAC/amd64: Define function to denormalize address EDAC/amd64: Define function to add DRAM base and hole EDAC/amd64: Define function to dehash address EDAC/amd64: Define function to check DRAM limit address EDAC/amd64: Remove goto statements EDAC/amd64: Define function to get Interleave Address Bit EDAC/amd64: Skip denormalization if no interleaving EDAC/amd64: Define function to get number of interleaved channels EDAC/amd64: Define function to get number of interleaved dies EDAC/amd64: Define function to get number of interleaved sockets EDAC/amd64: Remove unnecessary assert EDAC/amd64: Define function to make space for CS ID EDAC/amd64: Define function to calculate CS ID EDAC/amd64: Define function to insert CS ID into address EDAC/amd64: Define function to get CS Fabric ID EDAC/amd64: Define function to find shift and mask values EDAC/amd64: Update CS ID calculation to match reference code EDAC/amd64: Match hash function to reference code EDAC/amd64: Define function to get interleave address select bit EDAC/amd64: Add support for address translation on DF3 systems drivers/edac/amd64_edac.c | 710 ++++++++++++++++++++++++++++++-------- 1 file changed, 565 insertions(+), 145 deletions(-)