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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 14:43:22.4533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de1397cb-9cd6-4149-7fa2-08d9e65a5ca8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5402 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Hi all, This set adds support for AMD Family 19h Models 10h-1Fh and A0h-AFh. Patch 1 sets the "memory type" per DIMM. Patch 2 adds register offset and other minor changes introduced with these new models. Thanks, Yazen Link: https://lore.kernel.org/r/20211228200615.412999-1-yazen.ghannam@amd.com v3->v4: * Updated patch 1 to cache dram_type in struct umc. * Fixed uninitiliazed variable warning in patch 2. * Switched to a single register helper function. v2->v3: * Patch 1 completely reworked. * Patch 2 updated based on comments from William. Yazen Ghannam (2): EDAC/amd64: Set memory type per DIMM EDAC/amd64: Add new register offset support and related changes drivers/edac/amd64_edac.c | 113 +++++++++++++++++++++++++++++++------- drivers/edac/amd64_edac.h | 17 ++++++ 2 files changed, 109 insertions(+), 21 deletions(-)