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Wed, 2 Nov 2022 03:46:08 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , Subject: [PATCH 0/2] edac: xilinx: Added EDAC support for Xilinx DDR controller Date: Wed, 2 Nov 2022 14:16:06 +0530 Message-ID: <20221102084608.28894-1-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000C405:EE_|CH2PR12MB4309:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b3f5e92-d703-4564-2704-08dabcaeb275 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4pqqYs0qBR+an0ChRDIEbj81IaSquENQzfle+YrfWeGXSOVlNR9egMOrFv2/e6TId2kBkT5JjOHWbKTfX/M5QKw0E+E0vaTFErKGg15FKbBE84A70B4s7Llyvm+IC7Tecy6na95UhtN7bc4JWRWz8XwsP2KeO7sFg8pcjnPSIguF3tQDlKBNujQQgvhioweRzfE/xGtawJkBRGLJx1BC+tCAEG20AV0AnCFeWs2bNFklihfCNFEcLjaYV7hs+E9Vn58gX7Agsc3QYHoU7zNlHAR5GABTVRQR25hAeMtow9xV089977pAEDvy7ssFdn63WVXvKNFCYK7CKtcuFHh5rNzLGQ5vBnLpyXPIgadhVbNrEMw92FttvfqWX+5r1wOtPB3oOesNpMVsTXP7bOXjtSuXTLXEMhoN4IElzvc/wEfM+1A4Ka2HFRWD03Z565AjogrMFbZFrEksF9m40p7RNIO8PQF8xHadntFLXPrXq2vF0Wcb/qKEygy41hI3JEQ11U1SJ6at5TfeSl028Spw6xWzTiBgDZOCUs0d4c6bhvAyPf8JoHaZVjtGQrTB7g8I5ygFWvlEG5jlM+pCkMROdbzDUXRm3F+DisWifarS4p1vxDSFYYs3SdIH7y8NOFl8GwdzZuf+tKRLQA8zTQ00JEROUdUyBhwJeW9iZZjb6zBWmy3h5rZ13S7d8XhmTO0drKTNy+9R3ntEej6T5RZKqTA3h629rEgmO2RUl28eeVMQ87Ye4heM5kYNdxQsT7DtPHoZwmtQOUdZ9MvEsDZsGLT4+yiPiBfRtzMKgHUKRhmGbNVVuqsncw8eDAk59gWN X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(426003)(6916009)(44832011)(41300700001)(26005)(2906002)(336012)(2616005)(186003)(5660300002)(1076003)(4744005)(47076005)(83380400001)(36860700001)(54906003)(356005)(316002)(40460700003)(82740400003)(86362001)(478600001)(81166007)(82310400005)(70206006)(70586007)(8936002)(8676002)(40480700001)(36756003)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2022 08:46:13.0231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b3f5e92-d703-4564-2704-08dabcaeb275 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000C405.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4309 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X memory interfaces. It has four programmable NoC interface ports and is designed to handle multiple streams of traffic. Optional external interface reliability include ECC error detection/correction and command address parity. Adding edac support for DDR Memory controller. Shubhrajyoti Datta (2): dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC edac: xilinx: Added EDAC support for Xilinx DDR controller .../xlnx,versal-ddrmc-edac.yaml | 57 + MAINTAINERS | 7 + drivers/edac/Kconfig | 11 + drivers/edac/Makefile | 1 + drivers/edac/xilinx_ddrmc_edac.c | 1250 +++++++++++++++++ 5 files changed, 1326 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml create mode 100644 drivers/edac/xilinx_ddrmc_edac.c