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[v2,0/2] edac: xilinx: Added EDAC support for Xilinx DDR controller

Message ID 20221107062413.9642-1-shubhrajyoti.datta@amd.com (mailing list archive)
Headers show
Series edac: xilinx: Added EDAC support for Xilinx DDR controller | expand

Message

Shubhrajyoti Datta Nov. 7, 2022, 6:24 a.m. UTC 
The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X
memory interfaces. It has four programmable NoC interface ports and is designed
to handle multiple streams of traffic.

Optional external interface reliability include ECC error detection/correction
and command address parity.

Adding edac support for DDR Memory controller.


Changes in v2:
remove edac from compatible
Update the description
update the ddrmc_base and ddrmc_noc_base names
Update a missed out file
remove edac from compatible name
rename ddrmc_noc_base and ddrmc_base

Shubhrajyoti Datta (2):
  dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC
  edac: xilinx: Added EDAC support for Xilinx DDR controller

 .../xlnx,versal-ddrmc-edac.yaml               |   57 +
 MAINTAINERS                                   |    7 +
 drivers/edac/Kconfig                          |   11 +
 drivers/edac/Makefile                         |    1 +
 drivers/edac/xilinx_ddrmc_edac.c              | 1251 +++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   10 +
 6 files changed, 1337 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
 create mode 100644 drivers/edac/xilinx_ddrmc_edac.c

Comments

Borislav Petkov Nov. 8, 2022, 7:07 p.m. UTC | #1 
On Mon, Nov 07, 2022 at 11:54:11AM +0530, Shubhrajyoti Datta wrote:
> 
> The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X
> memory interfaces. It has four programmable NoC interface ports and is designed
> to handle multiple streams of traffic.
> 
> Optional external interface reliability include ECC error detection/correction
> and command address parity.
> 
> Adding edac support for DDR Memory controller.

Same question as in

https://lore.kernel.org/r/Y2qiRoiYepte/R4W@zn.tnic

How many memory controllers are there in Xilinx boards and how many EDAC
drivers can potentially be needed to run in parallel?

Also, this is an integrated memory controller, ZynqMP OCM is a on-chip
controller. Can we have a single xilinx_edac driver which contains
support for both memory controller types or are they completely
different?

Thx.
Shubhrajyoti Datta Nov. 9, 2022, 12:43 p.m. UTC | #2 
[AMD Official Use Only - General]



> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: Wednesday, November 9, 2022 12:38 AM
> To: Datta, Shubhrajyoti <shubhrajyoti.datta@amd.com>
> Cc: linux-edac@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>;
> devicetree@vger.kernel.org; michal.simek@xilinx.com; rric@kernel.org;
> james.morse@arm.com; tony.luck@intel.com; mchehab@kernel.org;
> robh+dt@kernel.org; krzysztof.kozlowski@linaro.org
> Subject: Re: [PATCH v2 0/2] edac: xilinx: Added EDAC support for Xilinx DDR
> controller
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Mon, Nov 07, 2022 at 11:54:11AM +0530, Shubhrajyoti Datta wrote:
> >
> > The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and
> > LPDDR4/4X memory interfaces. It has four programmable NoC interface
> > ports and is designed to handle multiple streams of traffic.
> >
> > Optional external interface reliability include ECC error
> > detection/correction and command address parity.
> >
> > Adding edac support for DDR Memory controller.
> 
> Same question as in
> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.
> kernel.org%2Fr%2FY2qiRoiYepte%2FR4W%40zn.tnic&amp;data=05%7C01%7
> Cshubhrajyoti.datta%40amd.com%7C5caa7f12a7ca4ede4b5e08dac1bc8ea7%
> 7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638035312878146800
> %7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL
> CJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=3%2B4
> KXoDza2kloKAWI27LT5VvZqQ5DQQMJm91s%2F5%2FrtQ%3D&amp;reserved
> =0
> 
> How many memory controllers are there in Xilinx boards and how many
> EDAC drivers can potentially be needed to run in parallel?


Platform	| Drivers / Controllers	|
------------------------------------------------------------ 
 ZynqMP	| Synopsys and OCM	|
Versal		| DDRMC and OCM	|


> 
> Also, this is an integrated memory controller, ZynqMP OCM is a on-chip
> controller. Can we have a single xilinx_edac driver which contains support for
> both memory controller types or are they completely different?

This patch series is for Xilinx Versal platform targeting DDR Memory controller.

As they are two different memory controllers (DDRMC and OCM) on different platforms (Versal and ZynqMP), 
so we cannot have a single driver.

> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeo
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> netiquette&amp;data=05%7C01%7Cshubhrajyoti.datta%40amd.com%7C5caa
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> 7C0%7C0%7C638035312878146800%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C300
> 0%7C%7C%7C&amp;sdata=JjvQZVXXAfJPS5tOj87QYzUdFhqzuZ3pO9Q%2BkQ
> 2IhTU%3D&amp;reserved=0