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Mon, 7 Nov 2022 00:24:17 -0600 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Mon, 7 Nov 2022 00:24:14 -0600 From: Shubhrajyoti Datta To: CC: , , , , , , , , , Subject: [PATCH v2 0/2] edac: xilinx: Added EDAC support for Xilinx DDR controller Date: Mon, 7 Nov 2022 11:54:11 +0530 Message-ID: <20221107062413.9642-1-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT047:EE_|CO6PR12MB5459:EE_ X-MS-Office365-Filtering-Correlation-Id: a8f34ab9-b0eb-430a-012d-08dac088c40d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DTQ44gSwNO7/nqZVPdjXezFpOQB0mvpIez5sBAcvJUqWNIFTRd5Lp8Q9iovYX+biE5gfX8VvnuhwFnkhxswKL5vz9wY9WE/v0jJyKH2/nhChYOVRP7KtaNhT3oiwLaU3uz0LuP7gmK/EQXfnTiKlfOJ/zHo0ECa+vVc2kbGs+4c1r/JmiaPLy+e+5gRr4eKFEU+G9tHMBfoXyqHlA1DNKz2DB2XPoVI5OT+ioVIS+uYnm42SRPj6pSJy2fghsMGe0v8ebBDBCbno8Z0SL3d+hLRkb+X6r7PxW4p3fsOdYInYC9A+fBhLcueJaznUfoUgOKfSL9bllsGNZrIaTRVbRI6fGeEQ9jmWUY5svM8NYFGWhXJE669R5r8qXanfhnh+auJsAjfJTUiWHd6jT6cqd9j1HKp2yP6ugasZHYP5D1wVXzUALaAWzyznAZQaA0P+7Obq70E3K1xAYyP7eC2AUg10LoH759AFQY7eMmePeHrerFWjpqnXvFPY5GlBPxcY8D0pBbPMRHqaAgIDf8/AlqXyj1z3IlNmcK0PqAuM1w7/Hbmq/T8Y9uqG693HEzKwOU9pBj9/JhAYb3mke2P5NBpq3KRW94045tZZ749icX0MOzk+pL/bNjHEbhxAML8NVocGOmzH0zha4B9MwncI6AnMvSmm9rHPxIYJbpXyJ6swMUcT/qBisH9PAyRVkGZ7IuMRYD+LMi7rda3/LJiEKLwpPjakb9mMF/4h/loASkDn1D1/SrwN9SSm843pcBqkbfttaaANNz5rs056fEZTaQQt2PVw0JiQdX5VSykdvp5yjA/pWUj7D+sw/uPKuyke X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(36756003)(36860700001)(86362001)(44832011)(5660300002)(2906002)(82740400003)(81166007)(356005)(47076005)(336012)(83380400001)(426003)(40460700003)(54906003)(316002)(70206006)(4326008)(70586007)(1076003)(186003)(2616005)(26005)(8676002)(6916009)(82310400005)(8936002)(41300700001)(6666004)(478600001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 06:24:46.2055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8f34ab9-b0eb-430a-012d-08dac088c40d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5459 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X memory interfaces. It has four programmable NoC interface ports and is designed to handle multiple streams of traffic. Optional external interface reliability include ECC error detection/correction and command address parity. Adding edac support for DDR Memory controller. Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names Update a missed out file remove edac from compatible name rename ddrmc_noc_base and ddrmc_base Shubhrajyoti Datta (2): dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC edac: xilinx: Added EDAC support for Xilinx DDR controller .../xlnx,versal-ddrmc-edac.yaml | 57 + MAINTAINERS | 7 + drivers/edac/Kconfig | 11 + drivers/edac/Makefile | 1 + drivers/edac/xilinx_ddrmc_edac.c | 1251 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 10 + 6 files changed, 1337 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml create mode 100644 drivers/edac/xilinx_ddrmc_edac.c