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Tue, 6 Dec 2022 17:36:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT032.mail.protection.outlook.com (10.13.174.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:19 +0000 Received: from titanite-35bahost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 11:36:17 -0600 From: Yazen Ghannam To: CC: , , , , Yazen Ghannam Subject: [PATCH v6 0/4] x86/mce: Support extended MCA_ADDR address on SMCA systems Date: Tue, 6 Dec 2022 11:36:03 -0600 Message-ID: <20221206173607.1185907-1-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|LV2PR12MB5797:EE_ X-MS-Office365-Filtering-Correlation-Id: f1b87cc3-43cb-4224-37ca-08dad7b062c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:36:19.5961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1b87cc3-43cb-4224-37ca-08dad7b062c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5797 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Hi all, This series of patches adds support for extended physical address on newer AMD CPUs. Patch 1 simplifies part of the MCA init path by reordering and combining some helper functions. This was shared by Boris during the discussion of v5 of this set. Patch 2 removes another MCA init helper function and merges it with the AMD MCA init code. Also, some other MCA init functions are reordered so that MCA is enabled after vendor init. This was shared by myself during the discussion of v5 of this set. Patch 3 moves the SMCA-specific parsing of the MCA_ADDR register into a separate helper function. This was originally submitted by Smita and reworked by Boris. The current version is unmodified from her v5 submission. Patch 4 adds support for the new location of the "LSB" field used when parsing MCA_ADDR. This was originally submitted by Smita, and I've rebased it on the first three patches. Thanks, Yazen Link: https://lore.kernel.org/r/20220412154038.261750-1-Smita.KoralahalliChannabasappa@amd.com Borislav Petkov (1): x86/mce: Cleanup bank processing on init Smita Koralahalli (2): x86/mce: Define function to extract ErrorAddr from MCA_ADDR x86/mce: Add support for Extended Physical Address MCA changes Yazen Ghannam (1): x86/mce: Remove __mcheck_cpu_init_early() arch/x86/include/asm/mce.h | 3 +- arch/x86/kernel/cpu/mce/amd.c | 16 ++--- arch/x86/kernel/cpu/mce/core.c | 100 +++++++---------------------- arch/x86/kernel/cpu/mce/internal.h | 44 +++++++++++++ 4 files changed, 74 insertions(+), 89 deletions(-)