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Mon, 16 Jan 2023 19:11:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Mon, 16 Jan 2023 19:11:09 +0000 Received: from onyx-7400host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 16 Jan 2023 13:11:08 -0600 From: Avadhut Naik To: , CC: , , , , Subject: [PATCH v1 0/3] Update SMCA Error Decoding for AMD EPYC Processors Date: Mon, 16 Jan 2023 19:10:59 +0000 Message-ID: <20230116191102.4226-1-avadnaik@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT027:EE_|CH3PR12MB7595:EE_ X-MS-Office365-Filtering-Correlation-Id: f438f4cf-d9d5-4d85-5b17-08daf7f56cfb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 19:11:09.2244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f438f4cf-d9d5-4d85-5b17-08daf7f56cfb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7595 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Modern AMD EPYC processors support Scalable MCA (SMCA) Error decoding. Currently however, on Family 19h and 1Ah based, AMD EPYC processors, not all SMCA errors are being decoded. This patchset attempts to address the very issue by updating error description structures and handling errata of some SMCA bank types. The first patch adds new error descriptions for various SMCA bank types while also rewording existing and removing unused error descriptions. The second patch handles the mismatch, encountered on some AMD CPUs, between the HWID read from the MCA_IPID register and the HWID expected by the kernel for XGMI Controller SMCA bank type during SMCA initialization. The third patch tackles the erratum no. 1384, encountered on Genoa and a few other CPUs due to bit reassignments in Control register of the Coherent Slave (CS) SMCA bank type. Avadhut Naik (2): x86/MCE/AMD: Add HWID Fixup for PCS_XGMI SMCA x86/MCE/AMD: Handle reassigned bit definitions for CS SMCA Yazen Ghannam (1): EDAC/mce_amd: Update SMCA bank error descriptions arch/x86/include/asm/mce.h | 1 + arch/x86/kernel/cpu/mce/amd.c | 50 +++++++++++++++++++++- drivers/edac/mce_amd.c | 79 +++++++++++++++++++++++++---------- 3 files changed, 107 insertions(+), 23 deletions(-)