[0/9] AMD MCA interrupts rework

Message

Yazen Ghannam May 23, 2024, 3:56 p.m. UTC

Hi all,

This set unifies the AMD MCA interrupt handlers with common MCA code.
The goal is to avoid duplicating functionality like reading and clearing
MCA banks.

Patches 1-3 are minor changes for issues found during testing.

Patches 4-9 are revised work of patches 6-12 from the following set:
https://lkml.kernel.org/r/[e-mail]

In addition to addressing review comments, I tried to reduce the amount
of refactoring to only what is functionally needed for fixes and
features. I still want to do a broader clean up, but I think that can
come later.

Patch 7 has a minor merge conflict with the following set:
https://lkml.kernel.org/r/[e-mail]

The sets do not depend on each other, so I thought to keep them
separate. But I can rebase this one on the other, if needed.

Thanks,
Yazen

Yazen Ghannam (9):
  x86/mce/inject: Only write MCA_MISC with user-set value
  x86/mce: Remove unused variable and return value in
    machine_check_poll()
  x86/mce: Increment MCP count only for timer calls
  x86/mce: Move machine_check_poll() status checks to helper functions
  x86/mce: Skip AMD threshold init if no threshold banks found
  x86/mce: Unify AMD THR handler with MCA Polling
  x86/mce: Unify AMD DFR handler with MCA Polling
  x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
  x86/mce/amd: Support SMCA Corrected Error Interrupt

 arch/x86/include/asm/mce.h         |   3 +-
 arch/x86/kernel/cpu/mce/amd.c      | 274 +++++++++--------------------
 arch/x86/kernel/cpu/mce/core.c     | 143 +++++++++------
 arch/x86/kernel/cpu/mce/inject.c   |   8 +-
 arch/x86/kernel/cpu/mce/internal.h |   7 +-
 5 files changed, 186 insertions(+), 249 deletions(-)


base-commit: 108c6494bdf1dfeaefc0a506e2f471aa92fafdd6