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[v2,00/16] AMD MCA interrupts rework

Message ID 20250213-wip-mca-updates-v2-0-3636547fe05f@amd.com (mailing list archive)
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Series AMD MCA interrupts rework | expand

Message

Yazen Ghannam Feb. 13, 2025, 4:45 p.m. UTC 
Hi all,

This set unifies the AMD MCA interrupt handlers with common MCA code.
The goal is to avoid duplicating functionality like reading and clearing
MCA banks.

Based on feedback, this revision also include changes to the MCA init
flow.

Patches 1-4:
General fixes and cleanups.

Patches 5-10:
Add BSP-only init flow and related changes.

Patches 11-15:
Updates from v1 set.

Patch 16:
Interrupt storm handling rebased on current set.

Thanks,
Yazen

---
Changes in v2:
- Add general cleanup pre-patches.
- Add changes for BSP-only init.
- Add interrupt storm handling for AMD.
- Link to v1: https://lore.kernel.org/r/20240523155641.2805411-1-yazen.ghannam@amd.com

---
Borislav Petkov (1):
      x86/mce: Cleanup bank processing on init

Smita Koralahalli (1):
      x86/mce: Handle AMD threshold interrupt storms

Yazen Ghannam (14):
      x86/mce: Don't remove sysfs if thresholding sysfs init fails
      x86/mce/amd: Remove return value for mce_threshold_create_device()
      x86/mce/amd: Remove smca_banks_map
      x86/mce/amd: Put list_head in threshold_bank
      x86/mce: Remove __mcheck_cpu_init_early()
      x86/mce: Define BSP-only init
      x86/mce: Define BSP-only SMCA init
      x86/mce: Do 'UNKNOWN' vendor check early
      x86/mce: Separate global and per-CPU quirks
      x86/mce: Move machine_check_poll() status checks to helper functions
      x86/mce: Unify AMD THR handler with MCA Polling
      x86/mce: Unify AMD DFR handler with MCA Polling
      x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
      x86/mce/amd: Support SMCA Corrected Error Interrupt

 arch/x86/include/asm/mce.h          |   7 +-
 arch/x86/kernel/cpu/common.c        |   1 +
 arch/x86/kernel/cpu/mce/amd.c       | 391 +++++++++++++-----------------------
 arch/x86/kernel/cpu/mce/core.c      | 322 ++++++++++++++---------------
 arch/x86/kernel/cpu/mce/intel.c     |  15 ++
 arch/x86/kernel/cpu/mce/internal.h  |   8 +
 arch/x86/kernel/cpu/mce/threshold.c |   3 +
 7 files changed, 332 insertions(+), 415 deletions(-)
---
base-commit: b36de8b904b8ff2095ece7af6b3cfff8c73c2fb1
change-id: 20250210-wip-mca-updates-bed2a67c9c57

Comments

Luck, Tony Feb. 13, 2025, 10:40 p.m. UTC | #1 
On Thu, Feb 13, 2025 at 04:45:49PM +0000, Yazen Ghannam wrote:
> Hi all,
> 
> This set unifies the AMD MCA interrupt handlers with common MCA code.
> The goal is to avoid duplicating functionality like reading and clearing
> MCA banks.
> 
> Based on feedback, this revision also include changes to the MCA init
> flow.

Apart from the nits I posed againt parts 5 & 15. LGTM.

Tested-by: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>

-Tony