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Tue, 22 Oct 2019 20:35:12 +0000 From: "Ghannam, Yazen" To: "linux-edac@vger.kernel.org" CC: "Ghannam, Yazen" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" Subject: [PATCH v2 4/6] EDAC/amd64: Use cached data when checking for ECC Thread-Topic: [PATCH v2 4/6] EDAC/amd64: Use cached data when checking for ECC Thread-Index: AQHViRgzqUXQe6JrSUGwHvuLMkPd5g== Date: Tue, 22 Oct 2019 20:35:12 +0000 Message-ID: <20191022203448.13962-5-Yazen.Ghannam@amd.com> References: <20191022203448.13962-1-Yazen.Ghannam@amd.com> In-Reply-To: <20191022203448.13962-1-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0501CA0024.namprd05.prod.outlook.com (2603:10b6:803:40::37) To BN7PR12MB2628.namprd12.prod.outlook.com (2603:10b6:408:30::20) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: dc1e556a-bd72-4df2-3be6-08d7572f563f x-ms-traffictypediagnostic: BN7PR12MB2724: x-ms-exchange-purlcount: 1 x-ld-processed: 3dd8961f-e488-4e60-8e11-a82d994e183d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3513; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20191018153114.39378-5-Yazen.Ghannam@amd.com v1 -> v2: * No change. rfc -> v1: * No change. drivers/edac/amd64_edac.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 2d8129c8d183..6b6df53e8ae7 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3200,31 +3200,27 @@ static const char *ecc_msg = "'ecc_enable_override'.\n" " (Note that use of the override may cause unknown side effects.)\n"; -static bool ecc_enabled(struct pci_dev *F3, u16 nid) +static bool ecc_enabled(struct amd64_pvt *pvt) { + u16 nid = pvt->mc_node_id; bool nb_mce_en = false; u8 ecc_en = 0, i; u32 value; if (boot_cpu_data.x86 >= 0x17) { u8 umc_en_mask = 0, ecc_en_mask = 0; + struct amd64_umc *umc; for_each_umc(i) { - u32 base = get_umc_base(i); + umc = &pvt->umc[i]; /* Only check enabled UMCs. */ - if (amd_smn_read(nid, base + UMCCH_SDP_CTRL, &value)) - continue; - - if (!(value & UMC_SDP_INIT)) + if (!(umc->sdp_ctrl & UMC_SDP_INIT)) continue; umc_en_mask |= BIT(i); - if (amd_smn_read(nid, base + UMCCH_UMC_CAP_HI, &value)) - continue; - - if (value & UMC_ECC_ENABLED) + if (umc->umc_cap_hi & UMC_ECC_ENABLED) ecc_en_mask |= BIT(i); } @@ -3237,7 +3233,7 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid) /* Assume UMC MCA banks are enabled. */ nb_mce_en = true; } else { - amd64_read_pci_cfg(F3, NBCFG, &value); + amd64_read_pci_cfg(pvt->F3, NBCFG, &value); ecc_en = !!(value & NBCFG_ECC_ENABLE); @@ -3522,7 +3518,7 @@ static int probe_one_instance(unsigned int nid) if (ret < 0) goto err_enable; - if (!ecc_enabled(F3, nid)) { + if (!ecc_enabled(pvt)) { ret = 0; if (!ecc_enable_override)