[1/2] rasdaemon: rename CPU_NAPLES cputype

Commit Message

Yazen Ghannam Nov. 1, 2019, 2:48 p.m. UTC

From: Brian Woods <[e-mail]>

Change CPU_NAPLES to CPU_AMD_SMCA to reflect that it isn't just NAPLES
that is supported, but AMD's Scalable Machine Check Architecture (SMCA).

  [ Yazen: change family check to feature check, and change CPU name. ]

Signed-off-by: Brian Woods <[e-mail]>
Signed-off-by: Yazen Ghannam <[e-mail]>
Cc: Chandu-babu Namburu <[e-mail]>
---
 ras-mce-handler.c | 10 ++++++----
 ras-mce-handler.h |  2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

Patch

diff --git a/ras-mce-handler.c b/ras-mce-handler.c
index fd3ef3b..016acae 100644
--- a/ras-mce-handler.c
+++ b/ras-mce-handler.c
@@ -55,7 +55,7 @@  static char *cputype_name[] = {
 	[CPU_KNIGHTS_LANDING] = "Knights Landing",
 	[CPU_KNIGHTS_MILL] = "Knights Mill",
 	[CPU_SKYLAKE_XEON] = "Skylake server",
-	[CPU_NAPLES] = "AMD Family 17h Zen1",
+	[CPU_AMD_SMCA] = "AMD Scalable MCA",
 	[CPU_DHYANA] = "Hygon Family 18h Moksha"
 };
 
@@ -192,8 +192,10 @@  static int detect_cpu(struct ras_events *ras)
 	if (!strcmp(mce->vendor, "AuthenticAMD")) {
 		if (mce->family == 15)
 			mce->cputype = CPU_K8;
-		if (mce->family == 23)
-			mce->cputype = CPU_NAPLES;
+		if (strstr(mce->processor_flags, "smca")) {
+			mce->cputype = CPU_AMD_SMCA;
+			goto ret;
+		}
 		if (mce->family > 23) {
 			log(ALL, LOG_INFO,
 			    "Can't parse MCE for this AMD CPU yet %d\n",
@@ -441,7 +443,7 @@  int ras_mce_event_handler(struct trace_seq *s,
 	case CPU_K8:
 		rc = parse_amd_k8_event(ras, &e);
 		break;
-	case CPU_NAPLES:
+	case CPU_AMD_SMCA:
 	case CPU_DHYANA:
 		rc = parse_amd_smca_event(ras, &e);
 		break;
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
index 94395eb..1ef7ef2 100644
--- a/ras-mce-handler.h
+++ b/ras-mce-handler.h
@@ -50,7 +50,7 @@  enum cputype {
 	CPU_KNIGHTS_LANDING,
 	CPU_KNIGHTS_MILL,
 	CPU_SKYLAKE_XEON,
-	CPU_NAPLES,
+	CPU_AMD_SMCA,
 	CPU_DHYANA,
 };